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FarmerPotato

TMS9900 data bus during instruction execution

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Has anybody documented the undefined behavior of the TMS9900 data and address buses when no memory cycle is happening?


I noticed this today while debugging a hardware glitch (unsuccessful so far): During the Add instruction, the databus repeats the two operand values.


I don't see this behavior documented in the TMS9900 manual. It seems like a nice feature to have. I guess it's the ALU "leaking" its values onto the data bus.


What does an Add instruction do? The sequence of operations is roughly:




instruction fetch
instruction decode
fetch source operand
fetch destination operand
internal ALU cycle (in this case, ADD)
store destination operand



Here is an observed sample case where the cpu adds 0010 + dec8 = ded8:


My registers:



WP 83E0
PC 7d32 (whole program from 7d00 to 7d80)
R0 0010
R5 A000



Bus observations (each row is at least 1 clock cycle):




ADDR DATA Signals Action
7d32 a540 MEMEN DBIN IAQ read instruction: A R0,*R5
???? xx40 decode
???? xx10 decode
83e0 xx10 MEMEN DBIN fetch R0 from 83e0
a000 dec8 MEMEN DBIN fetch dec8 from a000
???? xxc8 internal
???? xx10 internal
a000 ded8 MEMEM WE store result to a000



xx are the high byte I can't see (I'm reading the side port. I only see one half of an internal 16 bit bus read.)

?? are addresses I missed cuz I only grab the address when MEMEN is asserted.


The internal cycle values xxc8 and xx10 match the destination and source values.


I'll be taking more notes on other instructions.




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The data on the side-port has gone through the 16-to-8 mux, so that is not really the status of the 9900's data bus. Also, there are a lot of devices attached to the data bus, and if the CPU has its data bus in a high impedance state, other devices could be driving data on the bus lines.

 

As for the address bus, it is always an output from the 9900 and devices have to watch the various control signals to know when the address is valid. However, the 9900 has an output register for the address bus, so I would expect it to be stable between the various memory accesses.

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The chapter 4 in the "9900 Family Systems Design Handbook" actually mentions the states of the address bus and data bus during processing.

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The data on the side-port has gone through the 16-to-8 mux, so that is not really the status of the 9900's data bus. Also, there are a lot of devices attached to the data bus, and if the CPU has its data bus in a high impedance state, other devices could be driving data on the bus lines.

 

As for the address bus, it is always an output from the 9900 and devices have to watch the various control signals to know when the address is valid. However, the 9900 has an output register for the address bus, so I would expect it to be stable between the various memory accesses.

 

Right, I'm inferring the data bus from what I see on the mux. Which so far matches the low byte of all the ROM and PAD reads I have checked, but I need to check the logic for the mux to see what it does in all states.

 

I do suspect that some of the >10 values are the cpu holding its data bus in hi-Z just after a read cycle completes.

 

At some point I'm going inside the side port to bypass the mux and bring out the 16-bit databus.

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Posted (edited)

The chapter 4 in the "9900 Family Systems Design Handbook" actually mentions the states of the address bus and data bus during processing.

Thank you! I have read that now. It does document every detail.

 

*Note: The contents of the SD register remain latched at the last value written by the processor unless changed by the ALU. Therefore, during all memory read or ALU machine cycles the SD register and hence the data bus will contain the operand last written to the data bus by the CPU or the results of the last ALU cycle to have loaded the SD register.

 

Page 4-90, 9900 FAMILY SYSTEMS DESIGN

http://ftp.whtech.com/datasheets%20and%20manuals/Datasheets%20-%20TI/9900-FamilySystemsDesign-1stEdition/9900-FamilySystemsDesign-04-Hardware%20Design.pdf

Edited by FarmerPotato

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Thank you! I have read that now. It does document every detail.

 

 

How precise is the emulation in MAME in that regards?

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MAME does not emulate the bus states during internal cycles because there is no practical way to read them, unlike the real iron where you can attach an oscilloscope.

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