Overclocking the Stock 6502c: Is it Possible?

[JimDrew]

Might be interesting to scope pin 34 and see if there is any output.

 

Yeah, I guess comparing pins 34 and 36 would be a good thing. 
 

So, I looked at the early CPU board schematic.   I see how the HALT works.  This won't be a problem implementing.  It's just a simple condition.

 

Edited June 30, 2019 by JimDrew

[_The Doctor__]

Glad you took the time to look at it

[+mytek]

On 6/30/2019 at 1:05 PM, CharlieChaplin said:

Bob's XL-7 was taking part in the Abbuc hardware contest 2008. Attached are the pics and other stuff which Abbuc got for the contest...

hw2008-65816cpu-speeder-bob-woolley.zip 10.98 MB · 9 downloads

 

Thanks for posting the info. Was there ever a schematic or the CPLD code released as part of this?

 

On 6/30/2019 at 1:13 PM, JimDrew said:

Yeah, I guess comparing pins 34 and 36 would be a good thing. 

If you look at the schematic I posted earlier, you'll see that I don't have any connection to pin 34, or even show it on the CPU component since I considered it a no-connect with anything on the die.

 

[Kyle22]

Best Electronics has both the C014377 for $6.95. The C014806 is $8.00.

 

14377 = 6502B, 14806 = Sally.

 

[+mytek]

On 6/28/2019 at 9:22 AM, guus.assmann said:

Hello,

I have made a PCB, many years ago, that made it possible to use a 65C02 in the XL's or XE's.

And the XL7 is already in this forum, look at the attachments I put in.

Schematics and source code are there. Just needs some sorting out. There's "logic" in the file names.

 

BR/

Guus

 

For some reason I completely missed the schematics and the source code when you first posted this (my brain must have been stuck in a 'wait state'). Just now looking over what you uploaded, and it looks very thorough . Thanks for taking the time to upload all this great information ? .

 

LINK to that upload.

 

[JimDrew]

So, I re-spun the 65xxT board to have a jumper option for pins 34 and 36 (R/W) and added pin 35 (/HLT).  So, next month I will start doing some testing with an Atari 400 or 800 to see if the halt line works correctly.

 

[+mytek]

22 minutes ago, JimDrew said:

So, I re-spun the 65xxT board to have a jumper option for pins 34 and 36 (R/W) and added pin 35 (/HLT).  So, next month I will start doing some testing with an Atari 400 or 800 to see if the halt line works correctly.

 

That's great news Jim ? . I think a lot of people will be very interested in getting something like this. Any ballpark on the cost?

 

[Kyle22]

That project could work nicely with this:

 

 

[Lynxpro]

On 6/27/2019 at 9:55 AM, mytek said:

 

Not off topic as far as I'm concerned. Thanks for uploading ? .

 

I know this topic started out as an overclocking of the original Sally chip, but more and more that isn't looking to buy us much. So now it's morphed into changing processors to do acceleration, while still looking at an old school approach with the control logic, all the while attempting to keep the costs reasonable (not a lot of bells and whistles).

 

The information you provided appears to confirm what was talked about in the Atari Classics magazine article, where the 6502 is retained along with the addition of the 65816. Actually I'd just like to see a 65816 flying solo with a moderate speed up, and of course have the ability to downshift to 1.79 Mhz full time any time desired. Part of the plan would be to stick with 64K base RAM being shared, although that would be better served with higher speed static RAM. Since the 1088XEL and the soon to be released 1088XLD have fast SRAM already, that will be my initial target platform for any prototyping I'll be conducting. Please keep in mind that this is just a for fun exercise, so there might not be an end product coming out of this from my end, although the intention is to share methodology being applied in the experiments to follow.

 

 

I think it would be hilarious to use a 65816 upgrade on a disk drive... Then again, one could have a GUI load from there and use the SALLY in the Atari to still run all of the programs.

 

With all of the exotic GEOS Wheels upgrades over in C64 land, I'm surprised they haven't done that... run GEOS from an upgraded 1541/1571/1581.

[JimDrew]

On 8/19/2019 at 12:00 AM, mytek said:

That's great news Jim ? . I think a lot of people will be very interested in getting something like this. Any ballpark on the cost?

 

I am thinking in the $69 range... depending on quantities, maybe less.

 

Edited August 26, 2019 by JimDrew
typo!

[irich2]

On 8/18/2019 at 11:36 PM, JimDrew said:

So, I re-spun the 65xxT board to have a jumper option for pins 34 and 36 (R/W) and added pin 35 (/HLT).  So, next month I will start doing some testing with an Atari 400 or 800 to see if the halt line works correctly.

 

 

On 8/26/2019 at 3:27 PM, JimDrew said:

I am thinking in the $69 range... depending on quantities, maybe less.

 

 

Great news, Jim!!  Looking forward to the final product!!

 

[+mytek]

I think it's time to breathe some new life into this topic after sitting idle for a few years

 

And here is yet another version of...

 

 

The poor man's 7400 series accelerator (no CPLD or FPGA required).

 

And as noted, this is purely a theoretical concept, and may very well have many major holes in the design, not limited merely to the lack of Bus Transceivers. And to be perfectly honest, this one will likely never become a released design from me, being purely a personal project at this point.

 

At this point I also don't know if the ICS501 PLL chip clock input can actually reliably operate lower than the rated specification of 2 Mhz, so that may need to get moved to the 3.58 Mhz oscillator pin on the GTIA, although I'd prefer to use Antic's divided down output as shown to keep things simple.

 

The whole premise of this design is to swap out DRAM for high speed SRAM, and the OS/Basic Rom(s) for high speed EEPROM, so this is a bit more involved than just dropping in a Rapidus. I think to simplify this a bit, my initial target system will be an XEGS which only comes as 16K stock, and thus would benefit from the 64K SRAM boost, while only requiring removal of the two existing 16K x 4 bit DRAM chips to facilitate the change. Edit: I was thinking of my 600XL which only has 16K - the XEGS comes with 64K, but will still need to have the two DRAMs removed. It also has the OS and Basic combined on only one ROM that can be easily swapped out for a high speed EEPROM replacement.

 

In operation, via feedback from Antic and the MMU, high speed clocking can only occur when accessing the OS, built-in Basic, and the 64K of base RAM. All other operations are shifted down to 1X clocking. There are three clocking speeds available: 1X, 4X, 8X.

 

[Ricky Spanish]

something like this: https://www.hackster.io/news/65f02-is-a-100-mhz-drop-in-replacement-for-vintage-8-bit-computers-ef667b0ebed3

 

Edited August 8, 2022 by Ricky Spanish

[+mytek]

3 hours ago, Ricky Spanish said:

something like this: https://www.hackster.io/news/65f02-is-a-100-mhz-drop-in-replacement-for-vintage-8-bit-computers-ef667b0ebed3

That very thing was discussed in this topic back in 2019, with suggestions about making a SALLY drop-in based on it, but it never happened.

 

And with it being centered around an FPGA we probably wouldn't see anything coming from this until at least 2023 due to the chip shortage.

 

Hence the reason I'd like to make an accelerator based on discrete logic instead. It's purely out of a 'can it be done' curiosity on my part.

 

Edited August 8, 2022 by mytek

[reifsnyderb]

On 8/8/2022 at 1:35 PM, mytek said:

I think it's time to breathe some new life into this topic after sitting idle for a few years

 

And here is yet another version of...

 

 

The poor man's 7400 series accelerator (no CPLD or FPGA required).

 

And as noted, this is purely a theoretical concept, and may very well have many major holes in the design, not limited merely to the lack of Bus Transceivers. And to be perfectly honest, this one will likely never become a released design from me, being purely a personal project at this point.

 

At this point I also don't know if the ICS501 PLL chip clock input can actually reliably operate lower than the rated specification of 2 Mhz, so that may need to get moved to the 3.58 Mhz oscillator pin on the GTIA, although I'd prefer to use Antic's divided down output as shown to keep things simple.

 

The whole premise of this design is to swap out DRAM for high speed SRAM, and the OS/Basic Rom(s) for high speed EEPROM, so this is a bit more involved than just dropping in a Rapidus. I think to simplify this a bit, my initial target system will be an XEGS which only comes as 16K stock, and thus would benefit from the 64K SRAM boost, while only requiring removal of the two existing 16K x 4 bit DRAM chips to facilitate the change. Edit: I was thinking of my 600XL which only has 16K - the XEGS comes with 64K, but will still need to have the two DRAMs removed. It also has the OS and Basic combined on only one ROM that can be easily swapped out for a high speed EEPROM replacement.

 

In operation, via feedback from Antic and the MMU, high speed clocking can only occur when accessing the OS, built-in Basic, and the 64K of base RAM. All other operations are shifted down to 1X clocking. There are three clocking speeds available: 1X, 4X, 8X.

 

I was thinking about how this turbo cpu system would work.  

 

The Byte Attic videos (on youtube) show transceivers being used.  The W65C02 datasheet is rather contradictory in regards to the logic level voltages required and, quite frankly, some of the logic level voltages don't appear to be in any standard I've seen thus far.  This, of course, doesn't make much sense.  However, Western Design Center has instructions as to how to use the W65C02 in other computers, such as an Apple II series and they don't mention anything about needing transceivers.  (https://www.westerndesigncenter.com/wdc/AN-002_W65C02S_Replacements.php)

 

Another thought of mine has to do with timing in regards to ANTIC and it's /HALT signal.  I am thinking there may need to be some synchronization between ANTIC's /HALT signal and when turbo mode is disabled so that ANTIC can take over the bus.  Otherwise, a cycle may get cut short.  For all intents and purposes, without such synchronization, ANTIC and the CPU are on a different clock until ANTIC issues a /HALT.

 

There is also a good chance the PLL chip will have to be moved to the oscillator pin on the GTIA.  Given the cost of getting boards made, I'd just work with the PLL chip on the GTIA and figure out a way to synchronize ANTIC's /HALT with coming out of turbo mode.

 

A further simplification would be to use A15 as a "turbo select" line.  If A15 is low, /S4 is high, and /S5 is high then turbo mode is permitted.  While a compromise, this would eliminate the need to replace the ROM chips.

 

One of the big constraints here is cost.  My thought is that the parts cost for such a turbo system should be $30 or less in order to be competitive with the Rapidius.  This is keeping with a general rule that the retail price should be 3 to 4 times the cost of the raw materials.

 

Best Regards,

 

Brian

 

 

 

 

[+mytek]

Hi Brian

 

It was just a brain exercise for me, and not something I had really intended to pursue unless I was just sitting around idle, which is definitely not the case.

 

Interesting thoughts about synchronizing the clock. I wonder if @bob1200xl has any input, because he did make an accelerator that worked several years back, and before Rapidus.

[ijor]

4 hours ago, reifsnyderb said:

The W65C02 datasheet is rather contradictory in regards to the logic level voltages required and, quite frankly, some of the logic level voltages don't appear to be in any standard I've seen thus far.  This, of course, doesn't make much sense. 

 

I'm not sure what exactly doesn't make sense to you. The W65C02 can work directly at 5V and doesn't require level translation as long as it is powered at 5V. As the datasheet shows, it is possible to power the 65C02 at lower voltage levels. And in such cases, you do might need level shifters if you connect it to other logic working at 5V.

 

[reifsnyderb]

1 hour ago, ijor said:

 

I'm not sure what exactly doesn't make sense to you. The W65C02 can work directly at 5V and doesn't require level translation as long as it is powered at 5V. As the datasheet shows, it is possible to power the 65C02 at lower voltage levels. And in such cases, you do might need level shifters if you connect it to other logic working at 5V.

 

 

See page 24 of the datasheet.

 

https://eater.net/datasheets/w65c02s.pdf

 

Vih, for example, minimum voltages are as follows:

 

VDDx0.7

VDD-0.4

 

So, which is it?  Is the minimum voltage for a high input 3.5 VDC (5 * 0.7) or is it 4.6 VDC (5 - 0.4)???

 

That's what's confusing.  In the Byte Attic videos, he talks about having buffers due to concerns that the voltage level concerns.

 

Reading through some other posts, it's clear that some others are unsure about what this actually means.

 

 

 

 

 

 

[ClausB]

Maybe it's VDDx0.7 for BE, D0-D7, RDY, SOB, and it's VDD-0.4 forI RQB, NMIB, PHI2, RESB. At least that's how I read it until I looked at the next row!

 

[ijor]

55 minutes ago, reifsnyderb said:

See page 24 of the datasheet.

https://eater.net/datasheets/w65c02s.pdf

 

Vih, for example, minimum voltages are as follows:

VDDx0.7

VDD-0.4

 

So, which is it?  Is the minimum voltage for a high input 3.5 VDC (5 * 0.7) or is it 4.6 VDC (5 - 0.4)???

 

29 minutes ago, ClausB said:

Maybe it's VDDx0.7 for BE, D0-D7, RDY, SOB, and it's VDD-0.4 forI RQB, NMIB, PHI2, RESB. At least that's how I read it until I looked at the next row!

 

This

[ijor]

Btw. I think that in a way you are right. The datasheet is almost obviously, wrong, or at least misleading, about these minimum high voltage inputs. The chip is known to be TTL level compatible, as it is marketed as a pin compatible for NMOS parts. So the actual minimum high level should be much lower, at least very close to TTL levels. The hint is probably in the note numbered (1) in that page. Seems that these values are just statistical thresholds, not the actual requirement.

[reifsnyderb]

15 minutes ago, ijor said:

Seems that these values are just statistical thresholds, not the actual requirement.

This makes the most sense.  Given WDC's verification of the Apple IIe W65C02 substitution, it's the most likely explanation.

[+mytek]

BUMP

 

I just thought I'd add a link to where I got some of my initial ideas about swapping out a W65C02 for Sally: https://www.thebyteattic.com/2021/05/replacing-ataris-sally-cpu-with-modern.html

 

His video where he goes step by step through how Atari implemented a stock 6502 in the first 400/800 series machines is absolutely brilliant 👍

 

[reifsnyderb]

21 minutes ago, mytek said:

BUMP

 

I just thought I'd add a link to where I got some of my initial ideas about swapping out a W65C02 for Sally: https://www.thebyteattic.com/2021/05/replacing-ataris-sally-cpu-with-modern.html

 

His video where he goes step by step through how Atari implemented a stock 6502 in the first 400/800 series machines is absolutely brilliant 👍

 

 

Because of Western Design Center's instructions for using the W65C02 in other computers (https://www.westerndesigncenter.com/wdc/AN-002_W65C02S_Replacements.php), I am thinking that a slight modification to the Atari 400/800 6502B circuitry would allow the W65C02 to work without using the buffers thebyteattic guy adds.  (Slight changes would be needed because of the W65C02's inclusion of the BE line.)

 

To minimize the number of jumpers required to experiment, I am thinking about getting a test PBI board made just to try out a turbo mode scheme with the W65C02.  Such a test board would also require several jumpers to be ran from the system board to the PBI board.  Unfortunately, the PBI doesn't have enough nor the correct signals available to make for a PBI (or 1090) CPU upgrade, though.  The AS6C1008 chip works at 55ns.  So, it may be possible to use use it for the memory to get up to a 7 Mhz CPU speed.

 

If that works, I've been contemplating what a next generation 800XL board would look like with a turbo mode in it.  I just need to get some more time to look into this.

 

 

[ClausB]

8 hours ago, mytek said:

His video where he goes step by step through how Atari implemented a stock 6502 in the first 400/800 series machines is absolutely brilliant

Link please