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FarmerPotato

What if? Designing "Geneve 2020". Cool 3D views!

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1 hour ago, FarmerPotato said:

I should have asked, do you know git?

 

The tools I use are:

 

Cygwin, a unix-like shell on Windows. Use the installer to choose git tools.

Make - again, install with cygwin

 

Ralph's xdt99 to assemble.   Requires python, so install that

 

There is an example in the bios directory, tiny.a99

 

cd bios

make

 

 

Well... I have code on Git but I am not an expert.

 

The tool I use is a cross-compiler I wrote that runs on DOS. :) 

(I have been threatening myself to move it to GForth so it would be more portable.)

 

I think you have given me what I need to make a kernel however I will need to give you the cross-compiler and the source files and a batch file for you to build it as well.

 

I am a bit of a square peg I guess.

 

 

 

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2 hours ago, TheBF said:

Well... I have code on Git but I am not an expert.

 

The tool I use is a cross-compiler I wrote that runs on DOS. :) 

(I have been threatening myself to move it to GForth so it would be more portable.)

 

I think you have given me what I need to make a kernel however I will need to give you the cross-compiler and the source files and a batch file for you to build it as well.

 

I am a bit of a square peg I guess.

 

Right,  I remember you saying that.

 

There are a couple more things.

 

Take a look at the memory map in the Appendix I linked.

 

The interrupt and XOP tables are reserved, >0000 - >7E

ill be working on interrupt handlers above that chunk. 

>800 - >FFE is macrostore.

1000 is additional macro store (They are unified on one flash ROM.)

 

It would be best to start your code at >1400

Of course, with the reset vector pointing into it.
 

I can merge a binary with yours and replace those chunks. 

 

RAM is from >8000 - FFF8.

more on that 

safe to say 9000 upward is free. 
 

there is paging. Rom in 4000 to 7ffe. Ram in c000-fff8. More on that later if needed. 
 

 

 

Edited by FarmerPotato
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9 hours ago, FarmerPotato said:

 

IMG-1375.thumb.JPG.a88d288fb7fb5d559a3c2d6ff722364d.JPG

 

 


This is the Geneve 2020 prototype I've been working on.

 

 

😍 YEEESSS! 

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Thanks to the kindness and support of jbdigriz, I have cpus again.

 

I had two of his to test.

 

Then a surprise by speedy mail from China (est Nov 30, actually just 14 days)

And I found a seller in California.


For future comparison, here are the markings:

 

Markings on CPUs I have

TMS99105AJDL

P1  CM 9123 c 1981 TI 0408068 TAIWAN   ordered 2019.  6V applied, not ok?
P2  CM 8939 c 1981 TI EU02992 TAIWAN   
J1  MC 8925 US02240 c 1981 TI TAIWAN   where did I put it?
J2  QC8842 5817 c 1981 TI PHILIPPINES  
Q1  MC9230 c 1981 TI US03847 TAIWAN   
Q2  MC9230 c 1981 TI US03847 TAIWAN   
Q3  MC9230 c 1981 TI US03847 TAIWAN   



P polida2008 ebay
J jbdigriz   atariage
Q qsourceco_6 ebay

IMG-1386.thumb.JPG.6c512b7b4f655be27a9d524dd39cce05.JPG

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On 10/24/2020 at 1:04 PM, FarmerPotato said:

 

IMG-1386.thumb.JPG.6c512b7b4f655be27a9d524dd39cce05.JPG

 

All CPUs have checked out OK.  Including J1, which didn't show up for this family photo. And even P1 is ok, that one that got 6V applied to VCC. (now I have to check other chips around it...)

 

 

 

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F Po,

   How where you planning on doing memory?

   I've thought, that with plentiful cheap SRAM, it would be pretty easy to do a board with a single 4 or 16MB SRAM chip and put a logic glue chip around it to 'throw' away the pages you don't need? 

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5 hours ago, dhe said:

F Po,

   How where you planning on doing memory?

   I've thought, that with plentiful cheap SRAM, it would be pretty easy to do a board with a single 4 or 16MB SRAM chip and put a logic glue chip around it to 'throw' away the pages you don't need? 

There will be some SRAM. These are 256K x 16 bits super-fast 10ns, and cost $4, so, SRAM is $8/MB.   Vintage parts are 55ns (and... still $8/MB.)


I'm testing vintage chips tonight.  The BIOS memory card has 256K SRAM and 128K Flash ROM. (70 ns parts)

 

The main memory will be in removable 30-pin SIMM module pairs. The memory mapper will support 2MB, 8MB, or 32MB.

MDOS will occupy a 2MB slice.

 

 

 

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Wait what? You mean, I'll be able to test memory, by removing it from a socket and swapping, instead of desoldering from a multi-side board, who's thru whole and traces are known to lift, from an ugly look?   Wonderbar!

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42 minutes ago, dhe said:

Wait what? You mean, I'll be able to test memory, by removing it from a socket and swapping, instead of desoldering from a multi-side board, who's thru whole and traces are known to lift, from an ugly look?   Wonderbar!

Yes, it is going to use real socketed chips, vintage, wherever feasible.

The Flash ROM and PLDs are all socketed (use inexpensive TL866 to update) 

The SRAM does have to be soldered as it is 0.5".

 

I love the idea of popping out SIMM modules, when you decide you need to go from 8 to 32MB.

It became feasible when I found the connector at peconnectors.com and new modules sold at memoryx.com

 

And... our 11-year old built his first PC last month. Which means, popping in the CPU and the DDR4 modules. Just something so satisfying about installing what parts are still left for the owner to install. Since then he's been telling everybody who will listen, that they can do it, too. The funny thing is that the Dell PC case he was reusing, doesn't fit any ATX boards at all. So he's got a cardboard box instead. The cardboard box now sports one of the power button/wire harnesses that I just made for Geneve2020.

 

I'm procrastinating just now. Because I need to move corrections from the breadboard, into the real board, which means soldering bodge wire on SMD. No fun.

 

 

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Today I've got the CPU card accessing ROM and RAM over the backplane. It's running well. 

 

The memory is on a wire-wrapped card, so I can evaluate the bus signals before sending off for a PCB. The WW version is quite simplified.

Today I also imagined adding a 9902 to the wire wrap board. Here is the kind of planning I do before starting WW:

 

WireWrapLayout.thumb.PNG.ae4183bf799a92928eee55e3ccaacc85.PNG

 

It's made from bits of the main schematics, pulled into a new Kicad schematic. It's laid out in the kicad pcb, but intended for perf board. I try to label all the pins, and I can print all this on a sticky label. Not all the traces are drawn. The ones that are, try to follow a sensible path for pulling a wire.

 

As I build it, I highlight traces done.

 

Wire wrap forms a very durable system. They were typically used to make production units, until PCBs became very cheap and reliable. 

And yet you can unwrap a wire and make changes just as easily. It sure beats lifting pins and soldering wires onto a PCB. In fact, you know the little wires you see as corrections on PCB? Those are made specifically for wire-wrapping. Wire wrap has advantages over breadboard. You need similar attention to cable management, but you can't accidentally unhook a wire.

 

====

 

This will form a minimal-minimal system. Once it's in a PCB card, I can't hack on it so easily.  But it can run a BIOS and I can test communication over a serial port. With that, I can keep working on hardware or software while I wait for PCBs to get made.

 

The current roadmap:

 

Minimal system anticipated, made of 100x100 mm cards, on an 8-slot backplane:

  • CPU card
  • BIOS memory card
  • I/O card
  • Front Panel & Power PCB*

*has PSU, fans, & keyboard/mouse connectors (for I/O card)

Will run FORTH language, has 256K SRAM.

 

A full system would also have:

  • Video card
  • Sound card
  • Main 32MB memory & FPGA card
  • Front Panel SD card modules

Intended to run GPL and MDOS

 

In-between steps are:

  • Develop and test keyboard/mouse drivers
  • Resume work on SD modules. Cabled to I/O card.

 

Final system, made of 160x100 mm cards:

  • CPU and BIOS card
  • I/O card with second 9901
  • Main memory and FPGA
  • Video card
  • Sound card

For a possible 4-slot system with no expansion, the video&sound might be combined.

 

 

 

That's the current roadmap.

 

 

 

 

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