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Chilly Willy

XL/XE 4MB RAM Expansion

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I was pouting over the lousy 64KB of ram in my 65XE the other day and decided to look into expansion options. It's one of those without the ECI port, so it would need to be an internal unit. Looking at what was out there, I wasn't very happy. How about I try my own hand at it? Here's my initial thoughts on the matter.

 

zkcxvXA.jpg

 

The idea is 1) it must use the "standard" CIA PORTB for bank control, 2) it cannot interfere with the normal operation of any of the bits, and 3) it should support CPU/ANTIC bank control. I looked at the memory available online... what do you know, there's a 2Mx8 5V 45ns SRAM from Digikey for about $5. Two of them would fill out a full 8 bit bank select just peachy. But how do you get 8 bank address lines from the port without interfering with the operation of the bits? A latch comes to mind. And that's the main thing - a hex D-Type flip-flop. Clearing PB7 will clear the latch, so asserting the self-test ROM will just clear the latch. No problem there. I use PB6 as the flip-flop clock (latched on rising edge). So if this were in an XEGS, clearing PB6 enables the Missile Command rom, which wouldn't be an issue as long as the code to switch banks isn't in either the bank memory space or in the rom cart space. No problem there, either, especially on systems without Missile Command. I use PB5-0 as the inputs to the d-flip-flops... no problems there as long as the code to switch banks isn't in bank memory space, the cart space, or the OS ram space... so in the first 16KB; oh, and the ints are off unless you keep the int code and data in the first 16KB as well. Still not an issue. But how do I get 8 bank address bits from 6 latched bits. Well, just use PB2 and 3 as normal. The latched bits extend them from 2 bits to 8 bits. Use A21 and it's inverse to select one of the two sram chips, use PB4 and 5 along with A14 and A15 and /HALT to generate the other chip enable, a few gates for output enable and write enable and Bob's your uncle. The prices in the pic are from Digikey in single unit quantities for surface mount parts. A handful of bypass caps to round it out at less than $15 in parts... minus the board. That's gonna be the "fun" part. Been a while since I made a board.

 

I'll update as I get further along. Comments and suggestions are appreciated.

 

Edited by Chilly Willy
edit typos
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what happens when you write the value: 0x11xxx0 to PORTB?

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Nothing. You just switch the OS ROM to ram as usual. Unless you mess with PB6 and 7, it acts just like a normal 130XE would. And I already changed the title to 4MB... damn shift key. 😁

 

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0xxxxxx1 - SELF TEST

1xxxxxx0 - ROM OFF

0x11xxx0 - MapRAM

 

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19 minutes ago, xxl said:

0x11xxx0 - MapRAM

Oh, I read that as a hex constant, not 0-whatever-11-whatever-0. 😁

It would hold the latch clear, but otherwise act normally. So the self-test would find four banks of ram like the 130XE. Without using PB6 to latch the bits, it should be completely 130XE software compatible.

 

EDIT: I do see an issue on an XL - when the CPU or ANTIC accesses bank ram, it should disable onboard ram. The XE mapper does this, but the XL wouldn't. So the design above isn't XL compatible yet. I need to check into the easiest way to do that on an XL. I do have a couple 800XLs to go with my two 65XEs...

Edited by Chilly Willy
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Take a look at this historical reference about latching the OS, BASIC, and diagnostic PIA bits to seamlessly free them up for banking, seems very similar to your idea:

The idea here seems to be that all PIA bits retain their original function, as long as bit 4 is low. As soon as bit 4 is high, extended RAM is mapped into $4000-7FFF, and all bits 0123467 are usable for bank selection without affecting the previously set overloaded functions (OS, Selftest, BASIC), as long as the bank selection is done after bit 5 is high. This would result in 2048KB of extended memory.

 

To keep bit 5 for separate ANTIC banking, max extended memory is reduced to 1024k.

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21 minutes ago, Nezgar said:

Take a look at this historical reference about latching the OS, BASIC, and diagnostic PIA bits to seamlessly free them up for banking, seems very similar to your idea

Yeah, it's kinda the reverse of my idea - latching the other usage and then PORTB is just a bank, while my idea is latch the bank, then PORTB stays the normal function. Seems more compatible to me.

 

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Looking at schematics for the XL, 65XE, and 130XE, it seems the way to deal with internal RAM is to use an open collector driver to assert /EXTSEL on all models when the expansion memory is selected... that would be driven off the CE2 signal in my schematic.

 

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Hello Chilly Willy

 

- XEGS

- 64kB + 1024KB

- Separate ANTIC and CPU access

- Full software control over BASIC

- Full software control over OS ROM/RAM

- Full software control over Selftest

- Full software control over Missile Command

 

Check out this article by myself.  At the time I developed the upgrade, new 30 pin SIMMs for example were getting hard to find.  Today I would use more modern parts, like SRAM.  Unfortunately, I don't have the knowledge to prefect and really finish the upgrade (but it's been working fine in my XEGS ever since).  I had plans to eventually expand the upgrade to over 1MB (read: 4MB and 16MB) by using an extra address in the $D3xx range for the extra bits needed.

 

The only thing that really didn't want to work is the EXTEND command in BASIC XE.

 

Sincerely

 

Mathy

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Pretty cool. I love seeing all the different things people have come up with. I like that idea of using a SIMM for the memory. That was a great way to get a lot of DRAM for relatively less at the time.

 

Anywho, for the /EXTSEL line on my design, run the CE2 signal to the base of a typical NPN transistor. The 65XE would need the /EXTSEL pin on FREDDIE lifted (it's tied straight to 5V in the schematic), and soldered to the /EXTSEL from the expansion, along with a 3K ohm pull-up resistor. 800XL and 130XE systems already have the line pulled high with a 3K ohm resistor, so you would just solder line to it directly on those systems. Need to check the schematics for a 600XL, but I'd guess it's like the 65XE - just pulled straight to 5V.

 

Just checked... the 600XL schematics I found shows /EXTSEL connected to the expansion port and pulled high like it should... the 600XL has PBI? I did not know that...

 

Edited by Chilly Willy
more info and whoopsie

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One more change... I was thinking about how to minimize the amount of soldering needed, and where to put the board. Under the ANTIC or CPU seems like the common choice for memory and video cards like this. I'd still need to solder lines for all the PORTB signals... or would I...  If you're sitting under the ANTIC or CPU, you have all the lines, so just decode PORTB yourself. More parts... less soldering... it's a trade-off.

 

AfZ3S8J.jpg

So for another 74LS21, another 74LS00, and a 74LS374, you don't have to solder any lines to the PIA. The cost is negligible, so it's totally worth it. 😎

 

Yes, it also latches the direction bits, but that's no big deal. The direction bits get set once to $FF, and from then on you just store the PORTB bits. I don't see it being an issue. With this addition, the only line to solder is the /EXTSEL. I can see how XL ram boards worked in the expansion port on the back. This could also work for XEs with ECI... which I don't have on either of my 65XEs. Well, I do have my brother's old 800XL if I wanted to make a fully external version.

 

 

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