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Geneve wait state timing


mizapf

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Oh, sorry to hear. It should not be an effect of the tests, since they only used read accesses and no writes.

 

The Gotek uses the same image files as the Lotharek, as I remember, so you can try to open the hfe file in TIImageTool to check whether it is still OK.

 

The tests on timing4 read data from specific pages (00, 20, 40, 60, 80, a0, ba, c0, e0, e8, ec, f0) to give a hopefully clear result which parts of the page space have 0 wait states. This would be an interesting result that I could integrate in the implementation of the Genmod on MAME.

 

If you dare - but I can do without that one - for a final test you could pull the SRAM out of your Geneve board to see whether the Memex is used for the SRAM area. I could not find anything about cutting the SRAM select line, so I suppose that either the SRAM page area (e8-ef) of the Memex is never used, or it must be deactivated by dip switch, or it runs in parallel to the on-board SRAM.

 

Please give me a notice when you manage to get your system and the test running, or when you need information or assistance.

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Got things working again @mizapf

 

GMWAIT1 results on GenMod Geneve.  110 = 109 or 110,  100 = 99 or 100... I've never seen a 111 or 101...  I ran in each mode a few times, and the 9's show up as expected, in inconsistent spots.

 

TURBO OFF, TIMODE OFF

Pages 00-E0: 110

Pages E8-EC: 100

Page F0: 110

 

TURBO ON, TIMODE OFF

Pages 00-A0: 100

Page BA: 110

Pages C0-EC: 100

Page F0: 110

 

TURBO OFF, TIMODE ON

Pages 00-E0: 110

Pages E8-EC: 100

Page F0: 110

 

TURBO ON, TIMODE ON

Pages 00-20: 110

Pages 40-A0: 100

Page BA: 110

Pages C0-EC: 100

Page F0: 110

 

-----

 

Not sure why the floppy stopped booting... I suspect I put something back in a peb-slot that is bad in some way... I took all the cards out, and deoxit'ed and cleaned the edge connectors on the peb cards.  Finally took apart the corcomp floppy, to double check that my dead-bug genmod decoding chip hadn't dislodged and shorted... everything is good again, except it won't boot if my TIPI is installed. :(  The way I remember it, the only change from when it worked, to not working, was pulling the memex card out to check the dip-switches, putting it back in. I had the TIPI removed during that testing, and it was still removed when I started having the boot trouble. Maybe my back-plane has a small fracture or something... This system has always been critical of the slightest breath.  Might be time to buy another PEB. 

 

-M@

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  • 2 years later...
On 12/11/2019 at 6:55 PM, mizapf said:

Thanks, Matt. This is pretty interesting!

 

- Even though you have on-board DRAM, the pages 00-3F are used with 0 ws (turbo=1, timode=0). I really wonder how the DRAM feels like when it is treated with these 0-ws accesses. As I said, the traces to the DRAM are not cut (and cannot be cut), so it will react on accesses to 00-3f. As it seems, it must stay in sync with the Memex RAM ... somehow.

- The BA page access is not sped up (1 ws)

- As I guessed, with Turbo=1, TIMODE=0, the "additional wait state" feature is ineffective, at least for the 00-3F access. The even-numbered tests were using the additional wait state setting. As I said, the Genmod cannot at the same time suppress wait states and allow for additional wait states, as it cannot peek into the Gate array.

- The mirroring of BA is as expected.

 

I will provide one more (hopefully final) test to check the access to different page areas.

Michael,

 

I found this thread for the test programs, though haven't checked out the files on it to see if source was included or not.

 

I am not sure if it was ever communicated or not, but I know when Ron designed the cards, he had chips on the GenMod (and maybe Memex as well) that were I believe in the 20 ns speed range that did some testing before the Geneve was ready.  The chip(s)/logic, would block access to certain Geneve memory such that traces would not need to be cut and could be controlled by the switch control panel box.

 

Beery

 

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It's been a while since I've looked at the Genmod memory circuit.... I seem to recall that the DRAM data output/input could be controlled by CAS via the Genmod. There is also a variable voltage regulator added to the circuit.   I thought Ron added circuitry to safely disable the DRAM, when appropriate, and to inhibit/enable the Memex corresponding pages.  I have a Genmod on my work bench and if I get it working, I'll try to check the voltages and signals. 

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