Missalignement of VBLANK generated black.

[Windless]

Hi,

 

  according to 8bitworkshop and stella, the VBLANK bit if set to 1/0 affects the cathod ray 1 TIA Cycle avec it's commited on the bus by the CPU. Is this documented somewhere ? I couldn't find reference to this in the documentations I have.

 

Thanks,

Windless.

 

Test code :

	ldx #64
ScanLoop

	sta WSYNC
	SLEEP 20
	lda #$aa
        sta COLUBK
	lda #$34
        sta COLUBK
	lda #$aa
        sta COLUBK

	sta WSYNC
	SLEEP 20
	lda #$aa
        sta COLUBK
	lda #%00000010
        sta VBLANK
	lda #%00000000
        sta VBLANK

	sta WSYNC
        
	dex
	bne ScanLoop

Result :

 

https://8bitworkshop.com/v3.5.0/embed.html?p=vcs&r=TFpHAAAQAAAAAJFODB%2FcAQMEBQZ42KIAiqjKmkjQ%2B6kChQEGYQCFAgYiqQCFAKIlhQLKBREAhQGiQIUC6gYHqaqFCak0BmEG4QQPEAV%2FBSoFc8sFRaIeBb5MC%2FD%2FBh8GHwYfBh8GHwYfBh8GHwYfBh8GHwYfBh8GHwYfBh8GHwYfBh8GHwYfBh8GHwYfBh8GHwYfBh8GHwYfBh8GDADwAPA%3D

 

Edited December 26, 2019 by Windless