CorComp DSDD Disk Controller docs

[tdididit]

There is bit more errors in schematics and differencies between CC9900 revisions, including gluelogic.

I started building my sidecar CC9900 now basing on TMS2793 formatter chip.

At the moment waiting for pldanalyzer boards to rip PAL equations from PEB card I get from friend - TMS2793 CC9900

 

[RickyDean]

10 hours ago, tdididit said:

There is bit more errors in schematics and differencies between CC9900 revisions, including gluelogic.

I started building my sidecar CC9900 now basing on TMS2793 formatter chip.

At the moment waiting for pldanalyzer boards to rip PAL equations from PEB card I get from friend - TMS2793 CC9900

 

This will awesome, I can finally get a replacement set for one of my CC's

[+mizapf]

Are the CorComp controllers known to have a short floppy motor spinning time? I'm asking because the motor monoflop (74LS123) on both original and revised versions shows a 100k/47µF combo, while on the original TI controller we have a 200k/47µF.

 

This should have a visible effect: I suppose with a CC controller, the floppy motor only spins for about 2 secs, while it spins for 4 secs with the original controller.

[+mizapf]

Easy to check: If you have a CorComp controller, press Quit and check how long the floppy motor runs (after the beep; listen to the drive, maybe insert a noisy disk). If I use the given values, using a stopwatch I get about 1.4 secs for CorComp (3 secs for BwG/original TI controller).

 

BTW, the 2793-based controller is now working in MAME. I'll do the revised one today.

 

I'll call the original controller "ccdcc" (from its designation on the board, PEB-DCC), and the revised version the "ccfdc" (CorComp FDC Rev A).

[tdididit]

9 hours ago, mizapf said:

Easy to check: If you have a CorComp controller, press Quit and check how long the floppy motor runs (after the beep; listen to the drive, maybe insert a noisy disk). If I use the given values, using a stopwatch I get about 1.4 secs for CorComp (3 secs for BwG/original TI controller).

 

BTW, the 2793-based controller is now working in MAME. I'll do the revised one today.

 

I'll call the original controller "ccdcc" (from its designation on the board, PEB-DCC), and the revised version the "ccfdc" (CorComp FDC Rev A).

It is easy to check if you have PEB, but I don't have it and space to set it up. Thats why I am re-creating PEB cards for sidecar port

I think that longer spin time was set by OG controller designers to be sure that floppy got right rotation speed before formatter chip start to read anything.

 

[+OLD CS1]

1 hour ago, tdididit said:

I think that longer spin time was set by OG controller designers to be sure that floppy got right rotation speed before formatter chip start to read anything.

The drive makes that determination using the RDY line which has a few requirements before going active, including speed.

[+mizapf]

The RDY line of the drive (I suppose you refer to that one) is not guaranteed to signal full spin-up, as I had to learn. Some drives seem to signal RDY just for inserted disk. The spin-up is not a real problem for the controllers; they typically allow the drive to get into motion before starting the operations. Should the the drive still be too slow, reading will fail, and the controller retries several times before it signals an error.

 

The worst problem for a short motor spin time is that it could spin down during longer operations of the program, which means you get repeated additional spin-up times. During single operations (read sector etc.), the drive monoflop is retriggered in time, but it could happen while you assemble a longer file that the floppy stops running in the meanwhile.

 

I mean, it is just a matter of setting the value to the usual 200k, but I'd like to stay with the real thing, and maybe it is just the shorter spinning time that reminds people of the CorComps, hence my question to the forum who can check with a real CorComp card.

 

[+OLD CS1]

10 minutes ago, mizapf said:

The RDY line of the drive (I suppose you refer to that one) is not guaranteed to signal full spin-up, as I had to learn. Some drives seem to signal RDY just for inserted disk.

It is.  By spec, reading 5.25" drives the requirement is to have a certain number of rotations with a certain speed.  It is true, based upon TEAC FD55 specs quoted below, it does not necessarily guarantee full spindle speed:

 

 

 

(13) READY output signal
   (a) Level signal which indicates that the FDD is in ready state.
   (b) The FDD becomes ready state when all of the following four
       conditions are satisfied.
      i) The FDD is powered on.
      ii) Disk is installed.
      iii) The disk rotates at more than 50% of the rated speed.
      iv) Two INDEX pulses have been counted after item iii) is
          satisfied.
      Note: Pre-ready is the state that at least one INDEX
      pulse has been detected after item iii) is satisfied.
   (c) Required time for this signal to become TRUE after the start
       of the spindle motor is less than 730msec (G model) or 800msec
       (A, B, E & F model). However, if the spindle motor reaches
       the rated rotational speed whthin 400msec after the start,
       then the READY signal becomes TRUE.

 

[+mizapf]

Do we have Myarc DDCC-1 cards with a WD1772? The one I have uses a WD1770.

 

I am asking because I have some schematics here that say "1770 or 1772". The point is that the 1772 has different step rates, and maybe this requires a modified DSR. I can emulate this, but it does not make sense to offer a non-existing option.

 

Also, on the schematics there is an additional switch labeled "Turbo" (SW2). On my DDCC-1 there is no such switch, and it seems to have no effect for the DSR that I have. Does anyone know more about that switch?

[+Ksarul]

The turbo switch is a Michael Becker modification. I have seen cards with the 1770 and others the 1772. I don't think the DSR was different, although I think some of them had a lot more modifications on the board.

[atrax27407]

There are some mods to the Myarc DSR. I have a couple of EPROMs that allow for reduced head step rates.