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MikeV

ESD Hard & Floppy Controller

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I purchased a copy of that Hypercard software (HQ Stacks) a long time ago. It was released by McCann Software. The Forth card he was working on used the Forth Microengine chip. He was forced to cancel the card because the chip manufacturer cancelled the chip before it reached full production. No chips--no cards that can use it. I'm not sure what Mike McCann did with the prototype card he built. He passed the rights to the McCann software titles to Dee Turner, who kept them available until about ten years ago when sales had decreased to nothing.

Edited by Ksarul

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17 hours ago, Ksarul said:

I have a complete set of the developmental docs that were included with the card when I bought it from Tony Lewis about ten years ago. I don't think there were ever any ads/flyers for it, although there were a couple of blurbs on it from Asgard, as they were planning on bringing it to market at one point.

This is really very interesting information. I lost faith in most "new hardware" after the Cor Comp "Phoenix" fiasco. Some of it was apparently real. Is it possible that Asgard (Peripherals) was behind the proposed ESD card as well? They were extremely informed on its supposed development. It would have been in keeping with that rather long article by Chris Bobbit, wherein he addressed the various short-comings of the TI and  possible solutions. E.G. memory (AMS), video, etc.

 

It is always interesting to learn of new hardware developments for the TI. Apart from the HRD 4000B, do you have some specifics in the works, i.e. that you perceive as doable at this point?

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On 3/13/2020 at 4:57 PM, BeeryMiller said:

I've got two Geneve's setup with Myarc HFDC's with the DREM that uses a SD card.  I got away from spinning drives.  One of my Geneve's has a TIPI in it. In GPL/Rompage mode, I have full TIPI "hard drive like" access and speeds.  If someone was a good programmer, they should be able to rewrite the eprom code to load a System/Sys file from the TIPI to boot the Geneve.  Then, they would need floppy access to get to GPL mode as MDOS itself would not support the TIPI.

 

I have two TI-99/4A's setup.  One has a SCSI with a SCSI2SD interface with it configured to 7 x 256 MB drives.  The PEBox also has a TIPI in it as well.  It isn't getting too much use right now as I have been focusing on some other software for the TI-99/4A (separate topic elsewhere).  My other TI-99/4A has a sidecar TIPI w/ 32K.

 

 

Hi Beery,

 

This is good information. Do you know if it is possible for folk to interface a HFDC/ SD card on a TI? I had to google DREM as I had no idea what it meant. Is this it: DREM?

 

Do you know if it is possible to use SD drives with our SCSI? Thank you.

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Hi Beery,
 
This is good information. Do you know if it is possible for folk to interface a HFDC/ SD card on a TI? I had to google DREM as I had no idea what it meant. Is this it: DREM?
 
Do you know if it is possible to use SD drives with our SCSI? Thank you.
Scsi2sd works great with scsi

Sent from my LM-G820 using Tapatalk

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DREM replaces normal MFM drives and floppy drives. Your controller thinks it is a regular drive. It is a nice device, and the developer is VERY responsive to issues/feature requests.

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2 hours ago, MikeV said:

Hi Beery,

 

This is good information. Do you know if it is possible for folk to interface a HFDC/ SD card on a TI? I had to google DREM as I had no idea what it meant. Is this it: DREM?

 

Do you know if it is possible to use SD drives with our SCSI? Thank you.

Yes, the DREM replaces the MFM drives and the SCSI2SD replaces SCSI drives.  Makes backups a whole lot easier to just copy things from a SD flashdrive onto a PC folder.

 

The big issue is whether you can find a HFDC or SCSI controller.


Beery

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On 3/14/2020 at 6:43 PM, Ksarul said:

And it seems more of the TI TMS9650 chips have been coming out of the woodwork lately, as I found two sources with small numbers of them when I went searching today. That may help me get the card to the point of making some tests. . .

I see you want the TMS9650 for Tony Lewis’ math coprocessor card. How many chips did you find?
 

I’ve  been curious about this chip since reading the data book at SMU. It gets my imagination going.

 

It could be recreated in an FPGA.  which would also be overkill, as the whole math coprocessor could be implemented in FPGA plus a FORTH core too (J1A for example.)


My design philosophy is to use real chips, or no bigger FPGA than necessary to replace an old chip. Hard to comply with in this case because the TMS9650 needs 256 bytes = 2K bits of RAM, plus some bytes for registers.
 

that would be many separate chips if done in discrete logic (bunch of buffers or latches, a RAM, one GAL16V8 perhaps.)

 

(Bonus cred: use an original TI 2Kbit static RAM.)

 

I don’t know of a cheap, low end FPGA that has just 2K bits of RAM to replicate the TMS9650. But perhaps the full 256 byte RAM is unneeded?


 

I see harder-to-find Xilinx 95xx 5V parts in people’s 4A designs to date (NanoPEB for one.. Tipi @jedimatt42? Dragon’s Lair? @Tursi)


I’ve played with the Lattice MachX02 dev board (my first FPGA) The $5 3.3V MachXO2-640 is small-ish , has 18+5 Kbits of RAM, in a 48 or 100 pin QFN 0.5 mm pitch. But in the semi shortage,  it’s unobtainable for a year out. 
 

 I still think about the 3.3V ICE40HX1K as a “lower end” FPGA part for $5, and still that has 64Kbit of RAM onboard. It uses  OTP or external Flash (any cheap 25x series) Overkill. 
 

Whereas the E-Bus arbiter 74LS2001 could be done in a GAL16V8 ($1 new from Mouser). just it can’t do the exact 74LS2001 pin out with its stupid power pin placement (sorry, Cortex owners) but same package size. 

Background

 

I’ve learned about 3 vintage 9900 parts for multiprocessing: 

 

The 74LS2001 does bus arbitration between multiple COUs or DMA memory.  (Thanks @Ksarul for posting E-Bus.)

 

 The 9650 arbitrates internal access to its RAM among two ports, through the READY line, but assumes separate buses.
 

For two equal processors on one bus, the 9650 calls for a bus arbiter like the 74LS2001. For a coprocessor, (math, peripherals etc) there is no need for a shared bus. 


Finally , the 99105 has MPI lock out, to implement semaphores in test-and-set style. In a 99105 multiprocessor arrangement, you still need a bus arbitrator to keep the bus during MPI lock, during which the source operand is read, bus sits idle, then operand written to. ABS behaves like this  on the 9900 to implement test-and-set. In the 99105, ABS does assert MPI lock, alongside instructions Test and Set, Test and Clear Bit. 

I haven’t familiarized myself with the TMS9911 DMA controller, which seems to be available (though I’m skeptical.)

 

 


 

 

 

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41 minutes ago, FarmerPotato said:

I see you want the TMS9650 for Tony Lewis’ math coprocessor card. How many chips did you find?
 

I’ve  been curious about this chip since reading the data book at SMU. It gets my imagination going.

 

It could be recreated in an FPGA.  which would also be overkill, as the whole math coprocessor could be implemented in FPGA plus a FORTH core too (J1A for example.)

 

Whereas the E-Bus arbiter 74LS2001 could be done in a GAL16V8 ($1 new from Mouser). just it can’t do the exact 74LS2001 pin out with its stupid power pin placement (sorry, Cortex owners) but same package size. 

Background

 

I’ve learned about 3 vintage 9900 parts for multiprocessing: 

 

The 74LS2001 does bus arbitration between multiple COUs or DMA memory.  (Thanks @Ksarul for posting E-Bus.)

 

 The 9650 arbitrates internal access to its RAM among two ports, through the READY line, but assumes separate buses.

 

I haven’t familiarized myself with the TMS9911 DMA controller, which seems to be available (though I’m skeptical.)

 

On the 9650's I bought about a dozen of them, but the two sources (I bought from both to validate each source) both had plenty more of them (I don't know if they still have them though--I need to hunt them down again).

 

A 74LS2001 in a GAL would be VERY useful, even to Cortex people. Just design a little circuit card adapter to place below the chip and move the pins to where they need to be, and voila, Cortex people have viable access to all of the goodness of E-Bus. :)

 

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