Pokey delayed serial input capture

[ijor]

As Hias commented in other thread, Pokey doesn't capture the serial input at the optimum cycle. Ideally serial data should be captured at the middle of the bit cell. This allows for the maximum possible deviation between the rate transmitted by the peripheral and Pokey internal one. But Pokey instead performs the capture between 4.5 and 5 cycles later, depending on the phase of the serial input and the internal clock. This is not a big problem for the normal bit rates, but it is critical for the very high ones such as when using divisor 0.

Here it is a simulation waveform illustrating the worst case issue with divisor zero. The simulation is based on the original Pokey logic taken from my reverse engineered schematics:

 

 

The signals are the main clock, the external serial input in red, the internal synchronized serial input in yellow, and the first bit of the internal shift register in light blue. The counter at the top is a virtual counter that counts cycles since the internal serial input edge (this counter doesn't exist at the hardware).

The first vertical cursor, at the start of cycle #7, marks the center of the bit cell and is the ideal capture point. The period with divisor zero is 14 cycles. The second cursor at the start of cycle 12 shows when the bit is actually latched at the shift register, five cycles after the center of the cell. This five cycles, or four and a half, delay is constant regardless the divisor.