6502 bus access/timings on A8

[Xebec]

Hey folks - 

 

Where do you recommend I go to read up on how 6502 bus access and instruction timing works on the 8bit?    I know very basics - that instructions on 6502 are variable latency,  that the bus is shared with other chips, and ANTIC can effectively halt the CPU / executes it's own instructions.  

 

I'm specifically looking to learn / understand a little more about :

- How often can the 6502 read/write from main memory (typical use, and with "graphics off")

- Knowing that 6502 instruction timing is variable - learn about which instructions are bus limited and which aren't (are any?)

- Review the definitive list of how many clock cycles different instructions on 6502 take

- Also curious about the instruction set of ANTIC - what it can do 

 

Thanks!

John

[flashjazzcat]

You may find this interesting:

 

http://www.virtualdub.org/downloads/Altirra Hardware Reference Manual.pdf

 

[ivop]

I cannot find it that quickly, but there's a MOS publication that describes exactly what happens in all phases of the clock, each cycle, for each instruction, i.e. the whole state machine. I'm SURE it is somewhere on my backup drive, but I can't find it. Anybody knows which document I mean?

 

[Voxel]

19 minutes ago, ivop said:

Anybody knows which document I mean?

 

I had a copy by Rockwell.

 

Best I can point ot at the moment is: (scroll down)

http://archive.6502.org/datasheets/rockwell_r650x_r651x.pdf

 

[ChildOfCv]

4 hours ago, ivop said:

I cannot find it that quickly, but there's a MOS publication that describes exactly what happens in all phases of the clock, each cycle, for each instruction, i.e. the whole state machine. I'm SURE it is somewhere on my backup drive, but I can't find it. Anybody knows which document I mean?

 

There's also an online 6502 that you can watch in real time.  visual6502.org

[R0ger]

For basic ANTIC overview (also GTIA and POKEY) I suggest wikipedia: https://en.wikipedia.org/wiki/ANTIC

For instruction timing I use this page: https://www.masswerk.at/6502/6502_instruction_set.html

As for the buss access, you won't be too off if you assume every cycle reads or writes memory.

Altirra hardware reference manual (mentioned above) goes into depths into how it all works together. But the basic structure is - Antic does the DMA (and memory refreshes), CPU uses whatever cycles are left. In normal graphical mode, outside blank areas, 1 cycle goes to Antic, 1 cycle goes to CPU (with exceptions, of course). But that should give you rough idea.

Edited April 1, 2020 by R0ger