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TI-99/2 Thread


acadiel

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Stay tuned in this thread for a bunch of TI-99/2 information.

 

Ksarul knows what I'm talking about... :)

 

In the meantime, here are some tidits:

  • I am in possession of TI-99/2 unit #115.
  • This unit was originally going to be a Canadian demo unit, and is a almost production ready TI-99/2
  • The unit has 32K of ROM (attached), which Michael Zapf has confirmed is the same exact dumps as Klaus' 32K ROM
    • The system was originally supposed to have a 24K ROM (three EPROMs).  There is a 74LS139N logic chip installed 'dead bug' to enable bank switching at >4000 for 16K of the System ROM (8K at a time.)  I do have the pinouts of how this chip is hooked up.  I'll have to scan them.
    • The earliest specs for the computer said it would have 12K of ROM.  
  • The unit had two problems with it when I got it: 
    • 1) One of the bank switched >4000 ROMs was 'empty' - the TMS2564 voltage pin wasn't working, showing a null ROM.  Jumping bad pin 28(VCC) to 26 (also VCC) activated it. I programmed a new TMS2564 and installed it with the original sticker.
    • 2) The coupling 100nf glass capacitor near the power supply entry was shattered.  I bought a lot of 104 caps on eBay and installed a NOS one to keep the system authentic.
  • The system can run just fine off of a 7.5v, 2.5A DC power adapter.  The schematics for mine originally showed an AC PSU, but this most definitely uses a DC PSU, and has a 5V regulator inline.
  • The OLD CS1 and SAVE CS1 work just fine.  I was able to save and load to cassette.
    • The TI-99/2 does NOT tolerate stereo patch cables.  Use a mono one for both in/out
  • The system appears to have 4K of RAM.  If we can find a female cartridge connector, we might be able to PCB a RAM expansion.  We just have to figure out how much RAM the system will support in total.
    • The Memory map looks like this:
      • >0000->1FFF - System ROM
      • >2000->3FFF - System ROM
      • >4000->5FFF - System ROM (bank switched)
      • >6000->DFFF- My guess is that cart RAM/ROM expansion might live here (32K)
      • >E000->EFFF - System ram (4K)?
      • >F000->FFFF - Processor RAM and unused according to the memory map
  • The system has two custom IC's - CF40058 and CF40059.   These handle the Video Display Controller and I/O.   However, existing documentation for this system shows these two have different part numbers, CF40051 (I/O) and CF40052 (VDC).  I don't know which is which, but my guess is the 40059 is video (below the 9995) and 40058 is the I/O, because the dead bug for bank switching should be connected to the 40058.

 

Anyway, stay tuned to this thread.  I have some surprises coming.

 

94554460_1459967800844581_8638126835185483776_n.jpg

94436285_1583979475087466_2272913980286566400_n.jpg

jons_992_correct.zip

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Here is the dead bug reference For the bank switched >4000 ROM.  The Test points circled in the diagram are defined on the top (CF40058 chip) and the connections to the 74Ls139N are noted in the bottom box.

 

Note:  CF40058 is likely the I/O chip.  The only documentation available is for the CF40051, likely an earlier model.  The CF40051 shows pin #18 (TP1) being "S0/Keyboard Scan" and pin #20 (TP2) being "CRUCLKB (CRU Clock)."  How those play into bank switching, I don't know.  I do know that TP3 is a chip enable that will enable or disable that top EPROM.  I'm guessing that one of the cut traces goes to the bottom EPROM's chip enable, but I haven't metered that yet.

 

42AB14D3-93C7-4D0C-AC29-5E5CCAE86436.jpeg

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2 minutes ago, Ksarul said:

That connector is a 60-pin, so it would have the same specs as the PEB backplane connectors. I may even have a few of the female ones designed to crimp onto a flat cable in my random box-o-parts.

Would these work?

 

https://vetco.net/products/60-pin-card-edge-female-connector

 

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A question for Michael Zapf about the 99/2 emulation:

 

If we give the emulation 32K of RAM from >6000 to >DFFF, would the system would recognize all of it?  We can do that standard A=A+8 test to see if it does.

 

That'll be a good indication if we put the 32K chip between >6000 and >DFFF on a real system how it'll expand the RAM or not.

 

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Here is my best effort pinout for the 99/2, according to the schematic.  I've already found that the power supply (pre-regulator side) for the schematic is not  accurate for my system (the schematic shows an AC supply - I most definitely have an AC supply that is regulated down to 5V, and needs 7V DC minimum to get the regulator to run).  Seeing the 15V pins (33 and 34) that really aren't hooked to anything else makes me wonder if the 99/2's original PSU was a 15V supply, regulated down to 5V.  (I've been running 7.5V on mine without issue.)

 

I wonder how to properly plop a 5V 32K SRAM memory chip on this expansion bus.  In other words, does the >6000->DFFF space exist on this expansion board?  Anybody want to take a guess?

PIN	NAME
1	GND
2	GND
3	GND
4	GND
5	DCIN (5V)
6	DCIN (5V)
7	DCIN (5V)
8	DCIN (5V)
9	DCIN (5V)
10	DCIN (5V)
11	HORSYNC
12	COMP VIDEO
13	A8
14	A7
15	A6
16	A5
17	A4
18	A3
19	A2
20	A1
21	CRUOUT/A0
22	A9
23	NC
24	NC
25	A10
26	A11
27	A12
28	A13
29	A14
30	A15
31	D7
32	D6
33	15V
34	15V
35	D0
36	D1
37	D2
38	D3
39	D4
40	D5
41	CRUIN
42	CLKOUT
43	ROMEN
44	RESET IN
45	INT1 (low)
46	HOLDA
47	HOLD (low)
48	DBIN
49	MEMEN
50	W/CRUCLK (low)
51	RESET (low)
52	READY
53	NMI
54	CRTC CLK 3.35MHZ
55	VERSYNC
56	VIDEN
57	GND
58	GND
59	GND
60	GND

 

(Left rear of unit)                                                            (Right rear of unit)
                                            TOP OF UNIT
    +-------------------------------------------------------------------------------------------+
    | 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 08 06 04 02 | 
    | 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 09 07 05 03 01 |
    +-------------------------------------------------------------------------------------------+

 

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3 minutes ago, acadiel said:

I wonder how to properly plop a 5V 32K SRAM memory chip on this expansion bus.  In other words, does the >6000->DFFF space exist on this expansion board?  Anybody want to take a guess?

Why not? The address bus, data bus, MEMEM, and DBIN are there.

 

- Take one 2K SRAM for C000-DFFF

- Take one 4K SRAM for 8000-BFFF

 

Decode chip select for the 2K as (A0,A1,A2) = (1,1,0)

Decode chip select for the 4K as (A0,A1) = (1,0)

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18 minutes ago, mizapf said:

Why not? The address bus, data bus, MEMEM, and DBIN are there.

 

- Take one 2K SRAM for C000-DFFF

- Take one 4K SRAM for 8000-BFFF

 

Decode chip select for the 2K as (A0,A1,A2) = (1,1,0)

Decode chip select for the 4K as (A0,A1) = (1,0)

I didn't phrase my question correctly.  If this port is like the /4A's expansion port, the address space of >6000->7FFF is already decoded there.  You simply have to hook a SRAM up to the address pins and the data pins.

 

I wonder if they did this on the 99/2's expansion connector as well to keep the component count for cartridges low - if they already pre-decoded the address space, they could just plop a ROM on a PCB and get away with no chip select logic.

 

Edit, I found some notes here from one of the technical manuals.  However, these tech manuals were written at a time when this was a 12K ROM unit, not a 32K ROM unit.  

 

We have 4K RAM, so the whole of >E000->EFFF is 4K of RAM.  The picture below assumed 2K of RAM, so >E7FF downward would be counted as RAM, down to >6800.  That tells me the 32K "expansion" they originally wanted on the expansion bus (>6800->E7FF).   However, since they added the extra 2K of internal RAM, does that mean only 30K can be on the expansion bus?  (>6800->DFFF)?  Or, can it continue to "count down" two more kilobytes to be 32K from >6000->DFFF?

 

Anyway, I have the card edge connector and the 32K SRAM.  I just need some help designing a circuit if I do need to decode any address space here.  I figure we could start simple and just plop the whole 32K down from >6000->DFFF and see what happens.  There's nothing in that space anyway.  The last system ROM is located at >4000->5FFF.

expansionram.png

ROM.png

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I don't believe there is any similarity to the 99/4A decoding and its expansion port, and I cannot spot any selection line on the schematics. Fixed decoder lines would not be helpful, as they obviously conceived the address space to have ROM growing from the lower end and RAM growing from the upper end.

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That’s a very nice demo. 

 

So there only seem to be system ROM chips and no GROM chips. Is there any GPL in the TI-99/2 ?

I mean is the TI-Basic interpreter rewritten in assembly language?  If yes, this raises a couple of questions:

  • How does TI-Basic execution speed on the TI-99/2 compare with TI-Basic on the TI-99/4a ?
  • Did any source code for the TI-99/2 system ROMs ever appear?
  • Is the TI-Basic on the TI-99/2 a stripped down version of the 99/4a TI-Basic? I presume some commands do not exist (call color,..)
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This comprises my findings on the TI-99/2, which laid the base for the emulation in MAME. (Copied from ti99_2.cpp, 992board.cpp)

 

TI-99/2 driver

 

Drivers: ti99_224 - 24 KiB version
             ti99_232 - 32 KiB version

 

Codenamed "Ground Squirrel", the TI-99/2 was designed to be an extremely low-cost, downstripped version of the TI-99/4A, competing with systems like the ZX81 or the Times/Sinclair 1000. The targeted price was below $100. The 99/2 was equipped with a TMS9995, the same CPU as used in the envisioned flag ship 99/8 and later in the Geneve 9640. In the 99/2 it is clocked at 10.7 MHz. Also, the CPU has on-chip RAM, unlike the version in the 99/8. At many places, the tight price constraint shows up.
    - 2 or 4 KiB of RAM
    - Video memory is part of the CPU RAM
    - Video controller is black/white only and has a fixed character set, no sprites
    - No sound
    - No GROMs (as the significant TI technology circuit)
    - No P-Box connection

 

Main board

1 CPU @ 10.7 MHz (contrary to specs which state 5.35 MHz)
2 RAM circuits   (4 KiB instead of 2 KiB in specs)
3 or 4 EPROMs
1 TAL-004 custom gate array as the video controller
1 TAL-004 custom gate array as the I/O controller
and six selector or latch circuits

 

Connectors

- Built-in RF modulator, switch allows for setting the channel to VHF 3 or 4
- Two jacks for cassette input and output, no motor control
- Hexbus connector
- System expansion slot for cartridges (ROM or RAM), 60 pins, on the back

- Keyboard: 48 keys, no Alpha Lock, two separate Shift keys, additional break key.

 

Description

Prototypes were developed in 1983. Despite a late marketing campaign, including well-known faces, no devices were ever sold. A few of them survived in the hands of the engineers, and were later sold to private users. The Ground Squirrel underwent several design changes. In the initial design, only 2 KiB RAM were planned, and the included ROM was 24 KiB. Later, the 2 KiB were obviously expanded to 4 KiB, while the ROM remained the same in size. This can be proved here, since the console crashes with less than 4 KiB by an unmapped memory access. Also, the CPU is not clocked by 5.35 MHz as specified, but by the undivided 10.7 MHz; this was proved by running test programs on the real consoles. The next version showed an additional 8 KiB of ROM. Possibly in order to avoid taking away too much address space, two EPROMs are mapped to the same address space block, selectable by a CRU bit. ROM may be added as cartridges to be plugged into the expansion slot, and the same is true for RAM. Actually, since the complete bus is available on that connector, almost any kind of peripheral device could be added. Too bad, none were developed.

 

However, the Hexbus seemed to have matured in the meantime, which became the standard peripheral bus system for the TI-99/8, and for smaller systems like the CC-40 and the TI-74. The TI-99/2 also offers a Hexbus interface so that any kind of Hexbus device can be connected, like, for example, the HX5102 floppy drive, a Wafertape drive, or the RS232 serial interface. The 24K version seems to have no proper Hexbus support for floppy drives; it always starts the cassette I/O instead.

 

The address space layout looks like this:

    0000 - 3FFF:    ROM, unbanked
    4000 - 5FFF:    ROM, banked for 32K version
    6000 - DFFF:    ROM or RAM; ROM growing upwards, RAM growing downwards
    E000 - EFFF:    4K RAM
      EC00 - EEFF:  Area used by video controller (24 rows, 32 columns)
      EF00       :  Control byte for colors (black/white) for backdrop/border
    EF01 - EFFF:    RAM
    F000 - F0FB:    CPU-internal RAM
    F0FC - FFF9:    empty
    FFFA - FFFF:    CPU-internal decrementer and NMI vector

 

RAM expansions may be offered via the cartridge port, but they must be contiguous with the built-in RAM, which means that it must grow downwards from E000. The space from F0FC up to FFF9 may also be covered by expansion RAM. From the other side, ROM or other memory-mapped devices may occupy address space, growing up from 6000. One peculiar detail is the memory-mapped video RAM. The video controller shares an area of RAM with the CPU. To avoid congestion, the video controller must HOLD the CPU while it accesses the video RAM area. This decreases processing speed of the CPU, of course. For that reason, a special character may be placed in every row after which the row will be filled with blank pixels, and the CPU will be released early. This means that with a screen full of characters, the processing speed is definitely slower than with a clear screen. To be able to temporarily get full CPU power, there is a pin VIDENA at the video controller which causes the screen to be blank when asserted, and to be restored as before when cleared. This is used during cassette transfer.

 

Technical details

 

- HOLD is asserted in every scanline when characters are drawn that are  not the "Blank End of line" (BEOL). Once encountered, the remaining scanline remains blank.
- During cassette transfer, the screen is blanked using the VIDENA line. This is expected and not a bug.
- When a frame has been completed, the INT4 interrupt of the 9995 is triggered as a vblank interrupt.

- All CRU operations are handled by the second gate array. Unfortunately, there is no known documentation about this circuit.
- The two banks of the last 16 KiB of ROM are selected with the same line that is used for selecting keyboard row 0. This should mean that you cannot read the keyboard from the second ROM bank.

 

I/O map (CRU map)

0000 - 1DFE: unmapped
1E00 - 1EFE: TMS9995-internal CRU addresses
1F00 - 1FD8: unmapped
1FDA:        TMS9995 MID flag
1FDC - 1FFF: unmapped
2000 - DFFE: unmapped
E000 - E00E: Read: Keyboard column input
E000 - E00A: Write: Keyboard row selection
  E00C:        Write: unmapped
  E00E:        Write: Video enable (VIDENA)

E010 - E7FE: Mirrors of the above
E800 - E80C: Hexbus
    E800 - E806: Data lines
    E808: HSK line
    E80A: BAV line
    E80C: Inhibit (Write only)

E80E: Cassette

  

ROM dumps

 

Although these machines are extremely rare, we were lucky to get in   contact with users of both console variants and got dumps from their machines. The ROMs contain a stripped-down version of TI BASIC, but without the specific graphics subprograms. Programs written on the 99/2 should run on the 99/4A, but the opposite is not true in general.

 

Original implementation: Raphael Nabet; December 1999, 2000

    Michael Zapf, May 2018

    References :
    [1] TI-99/2 main logic board schematics, 83/03/28-30
    [2] BYTE magazine, June 1983, pp. 128-134

 

 

Emulation of the CRT Gate Array of the TI-99/2

Video display controller

RF-modulated, composite output
for standard black/white television

 

Selectable channel 3 or 4 VHF

625 lines for US markets
525 lines for European markets

Display: 24 rows, 32 columns

 

The controller accesses ROM and RAM space of the 9995 CPU. It makes use of the HOLD line to gain access. Thus, the controller has DMA control while producing each scan line. The CPU has a chance to execute instructions in border time, horizontal retrace, vertical retrace. In order to get more computing time, a special character (BEOL - blank end of line) is used to indicate the last drawable character on the line. After this character, the buses are released.

 

24K version: BEOL = any character from 0x70 to 0xff
32K version: BEOL = any character from 0x80 to 0xff

 

CRU Bit VIDENA: disables the scan line generation; blank white screen

Clock: 10.7 MHz

Scanline refresh:
- Pull down HOLD
- Wait for a short time (some dots)
- Use row, column, dot_line counters
  - Get the value c at 0xEC00 + row*32+col
  - Get the byte b from 0x1C00 + c*8 + (dot_line%8)
  - Push the byte to the shift register
  - Get the bits for the scanline from the register

 

EF00: Control byte: xxxx xTBS

T: Text color (1=white)
B: border color (1=white)
S: Background color (1=text color, 0=inverted)

 

Counters:

dotline 9 bit
after reaching 261, resets to 0

224..236: Top blanking
237..261: Top border
000..191: Display
192..217: Bottom border
218..220: Bottom blanking
221..223: Vert sync

 

dotcolumn 9 bit
increments every clock tick until reaching 341, resets to 0, and incr dotline

305..328: Left blanking
329..341: Left border
000..255: Display
256..270: Right border
271..278: Right blanking
279..304: Hor sync
 

Later versions define a "bitmap mode". [2] There are no known consoles with this capability, and it would require at least 6 KiB of RAM.

EF00: Control byte: xxxx xCBM
C : character color (1=white)
B: border color (1=white)
M: bitmap mode (1=bitmap)

 

[1] Ground Squirrel Personal Computer Product Specification
[2] VDC Controller CF40052

 

Emulation of the I/O Gate Array of the TI-99/2 [3]

The I/O controller is a TAL004 Low Power Schottky-TTL bipolar Gate Array that provides the interface between the CPU, the keyboard, the Hexbus, and the cassette interface. It delivers memory select lines for use by the CPU and by the VDC. It also offers a synchronized RESET signal and a divider for the CPU clock (which is seemingly not used in the real machines).

 

It is mapped into the CRU I/O address space at addresses E000 and E800, as listed above

 

[3] I/O Controller CF40051, Preliminary specification, Texas Instruments

 

 

Edited by mizapf
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Thank you for providing this, makes a very interesting read and interesting machine I must say.

More as anything else the 99/2 needs an F18a upgrade I’d say, just kidding ?

 

Was the 99/2a TI-Basic specification or any other 99/2 specifications ever released?

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9 hours ago, retroclouds said:

That’s a very nice demo. 

 

So there only seem to be system ROM chips and no GROM chips. Is there any GPL in the TI-99/2 ?

I mean is the TI-Basic interpreter rewritten in assembly language?  If yes, this raises a couple of questions:

  • How does TI-Basic execution speed on the TI-99/2 compare with TI-Basic on the TI-99/4a ?
  • Did any source code for the TI-99/2 system ROMs ever appear?
  • Is the TI-Basic on the TI-99/2 a stripped down version of the 99/4a TI-Basic? I presume some commands do not exist (call color,..)

The speed is much faster.  The standard For X=1 to 10000;print x loop runs much faster. 
 

We have the hex dumps for the roms.  At least the 32K ones.  I don’t know if source exists.  I’ve spoken with all four parties that programmed the ROM software.  Three do not have the source.  The fourth is not sure what they have, and won’t know until they go back home (from their second Vacation home) in June.
 

And yes, it’s stripped down.  All screen character definition, color, and sound is taken out.  There is added PEEK, POKE, and MHCL (execute machine language) instructions.  I’m sure if someone disassembles they rom, they can compare the BASIC tokens to the 99/4A. 
 

If someone has any thoughts on solving why the unit can’t stand the mic and earphone plugs being plugged in at the same time, l’m all ears.  I keep getting an Internal Error when I have both plugged in to the battery operated cassette.

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2 hours ago, acadiel said:

If someone has any thoughts on solving why the unit can’t stand the mic and earphone plugs being plugged in at the same time, l’m all ears.  I keep getting an Internal Error when I have both plugged in to the battery operated cassette.

Peering at your very clear circuit pics, the two signal lines seem to head to that slide switch, function unmarked on the rear of the case. Is that a double-throw, center off, or just a DPDT but the handle is centered? Probably it's the channel 3/4 selector. The solder joints to the jacks do not seem very solid. That capacitor you replaced lays between them, that and the switch might be unrelated to cassette I/O, but their proximity to the jacks caught my eye. Lastly, on the foil side, the pad to the left of the switch is unsoldered, that may head to the RF modulator. A few other solder joints look dicey, but that may be an artifact of the angle or lighting.

 

Maybe, maybe not, he said with certainty! :roll:

 

When all else fails, I apply my best Baleful Glare. ;)

-Ed

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