Jump to content
pcrock

Please HELP with 2 in 1 8K DIY CART

Recommended Posts

17 hours ago, ChildOfCv said:

"Works" and "Correct" are not necessarily the same thing.  From Fairchild's TTL design notes:
 

 

Hi friend. Once more thanks for replying. I know and I understand you are right about the TTL information you told us so I'm going to change my answer. What I meant is that this cartridge has been running Atari games for the past 37 years without ever failing. Which means that for this purpose, at least, this circuit works correctly in the way it is designed even if it is a weird thing.
I have another older PCB whose design is also like this with these floating pins.
But now you advised us about the question, I found a lot of other circuits here that matches exactly as you sayd! It haves the pin 4 and 5 conected together !
Once more I hane no words to thank you all for helpping me here!

Share this post


Link to post
Share on other sites
On 9/8/2020 at 7:04 PM, ChildOfCv said:

Makes me wonder how this board ever worked

I have seen that before, it is not uncommon for 70's / early 80's circuits. Depending upon the technology of fabrication of the chip, the emitters at input pins are biased enough to pull up the pin. one "advantage" of leaving the pin float was to save one pin in the fan-in/fan-out budget, and such mindset  was problably very live in the head of the enginners that designed the board. 

I would not rely on that, though, for the same reasons you have exposed 😆!

 

  • Like 1

Share this post


Link to post
Share on other sites
7 horas atrás, alex_79 disse:

WOOOOOOOWW !!! alex_79 !!! O Tapper v3 que você me enviou hoje está funcionando MUITO BEM !!!!!!!!!!!!!!!!!!!!
Sinto muito pelas fotos ruins, mas minha placa ATARI 2.6K está conectada a um dispositivo CRT !!
Estou mandando as fotos !!!
Muito obrigado aos amigos alex_79 e Thomas Jentzsch por me ajudarem na conversão de bankswitching para minha prancha brasileira !!! E obrigado a todos pela atenção em mim e nos meus problemas !!!!!

 



 

WhatsApp Image 2020-09-09 at 21.13.24.jpeg

WhatsApp Image 2020-09-09 at 21.09.47.jpeg

WhatsApp Image 2020-09-09 at 21.10.15.jpeg

WhatsApp Image 2020-09-09 at 21.11.17.jpeg

Edited by pcrock

Share this post


Link to post
Share on other sites

I'm glad it finally worked!

So it seems that the bankswitch on this board doesn't work reliably if the code that accesses the hotspot is being run from RAM. In the last version of "Tapper" it has been changed to run from ROM.

Edited by alex_79
  • Like 1

Share this post


Link to post
Share on other sites
19 minutes ago, Thomas Jentzsch said:

That's pretty odd. Any idea why this is happening?

Just to report. I don't know if this has to do with the problem but on this circuit, pins 4 and 5 of the LS00 are soldered together.

Share this post


Link to post
Share on other sites
11 hours ago, Thomas Jentzsch said:

That's pretty odd. Any idea why this is happening?

I guess it's a timing issue: the address lines don't switch state all at the same time, and the logic gates themselves add delay to some of the signals too. When accessing the hotspot from RAM, A12 stays unset, and maybe during the transition of the remainig bits  between the valid hotspot address and the valid next instruction one, a pattern corresponding to the other hotspot (or the "illegal" state of the latch) briefly appears on the bus, messing the bankswitch.

 

This is just my naive theory, so don't take my word on it!
I'm able to trace the circuit and reconstruct the truth table based on how the logic gates are wired, but understanding what happens during the transients is well beyond my skills.

 

Share this post


Link to post
Share on other sites

Got you. The floating pin is not responsible for this, right?

Share this post


Link to post
Share on other sites

It doesn't change the truth table: in both cases (pin 4 floating or connected to pin 5) the gate acts as an inverter for the signal on pin 5.

 

Whether it affects the timing during the transient, I have no idea.

 

Share this post


Link to post
Share on other sites
1 hour ago, Thomas Jentzsch said:

Got you. The floating pin is not responsible for this, right?

As I told before, this is not the circuit with the floating pin. The board I test the roms haves the pins 4 and 5 connected together. 

Share this post


Link to post
Share on other sites
50 minutes ago, alex_79 said:

It doesn't change the truth table: in both cases (pin 4 floating or connected to pin 5) the gate acts as an inverter for the signal on pin 5.

 

Whether it affects the timing during the transient, I have no idea.

 

I think the problem is that unless it's accessing ROM on the instruction following the bank switch, A5 and A6 will still "jiggle" the flip-flop until A10, A9, or A7 finally trickle through their path.

A12 is literally the only way a cartridge knows it's being read.  But for the bank switch scheme, it depends on NOT A12, meaning that it can only guess that the access is happening.

 

Edit 2:  Even A12 isn't good enough.  The next instruction after a bank switch needs to be in an address range that has both A5 and A6 clear.  So, xx0x, xx1x, xx8x, or xx9x.  This will keep A5 and A6 low until A12, A10, A9, or A7 can finish shutting down the bank switch select logic.

I think if you want a reliable flip-flop, you need a circuit that bases the toggle on an edge trigger instead of this level-triggered crap.

Edited by ChildOfCv
  • Like 2

Share this post


Link to post
Share on other sites
3 hours ago, ChildOfCv said:

The next instruction after a bank switch needs to be in an address range that has both A5 and A6 clear.  So, xx0x, xx1x, xx8x, or xx9x.  This will keep A5 and A6 low until A12, A10, A9, or A7 can finish shutting down the bank switch select logic.

Weird. In the Tapper rom that seems to work fine on this board, the next instruction is at $fff9, so both A6 and A5 are HIGH.

tapper_fa0.thumb.png.f6babf6d123c2cd1051e8562a6cc62da.png

 

 

I didn't include it in the schematic (as my goal was just to determine the truth table), but in the pics there's a small ceramic capacitor (unknown value) between pins 10-11 of the 74LS00 and GND.


Could a cap placed there help filtering out transient variation of the /R and /S inputs due to A5 and A6?
And, if so, could it be that it works when A12 pulses LOW, but it's not enough when A12 is steady LOW because the effect of the other signals (A9,A10,A7) are delayed by the extra gate (of the 74LS10) they go through compared to A12?

Sorry for the likely dumb questions. As I've said I only have very basic knowledge about this stuff, but I find it very interesting nonetheless.

  • Like 2

Share this post


Link to post
Share on other sites
2 hours ago, alex_79 said:

Weird. In the Tapper rom that seems to work fine on this board, the next instruction is at $fff9, so both A6 and A5 are HIGH.

Hmmm.  It may be the capacitance of the outputs that keeps it alive long enough for A12 to disable it then.  But for best reliability, I'd place the bank switch where A5 and A6 are both 0 instead of 1.

2 hours ago, alex_79 said:

I didn't include it in the schematic (as my goal was just to determine the truth table), but in the pics there's a small ceramic capacitor (unknown value) between pins 10-11 of the 74LS00 and GND.

This may interfere with state changes somewhat, but I bet its main purpose is to make sure the power-on state of the bank switch is always 0.

  • Like 2
  • Thanks 1

Share this post


Link to post
Share on other sites
On 9/11/2020 at 9:30 AM, alex_79 said:

Weird. In the Tapper rom that seems to work fine on this board, the next instruction is at $fff9, so both A6 and A5 are HIGH.

tapper_fa0.thumb.png.f6babf6d123c2cd1051e8562a6cc62da.png

 

 

I didn't include it in the schematic (as my goal was just to determine the truth table), but in the pics there's a small ceramic capacitor (unknown value) between pins 10-11 of the 74LS00 and GND.


Could a cap placed there help filtering out transient variation of the /R and /S inputs due to A5 and A6?
And, if so, could it be that it works when A12 pulses LOW, but it's not enough when A12 is steady LOW because the effect of the other signals (A9,A10,A7) are delayed by the extra gate (of the 74LS10) they go through compared to A12?

Sorry for the likely dumb questions. As I've said I only have very basic knowledge about this stuff, but I find it very interesting nonetheless.

Today I made a discovery!
I found out that of all these converted roms, centipede doesn't work on one of my consoles!!

All roms converted by friend alex_79, work on 2 consoles that I have that use TIA C010444 (and also on another one that uses UM6526N) but the Centipede does not work on the console that I have that uses TIA UM6526N.

All other roms work on all three consoles.

That is no matter to me, I plan to change TIA UM6526 to KSC131 or C010444 but is a curious thing.
I also found that the original ThunderGround (By Sega) (4K) game doesn't work on this console either.

When I start, all lives die instantly one after the other and the game is over. Hundreds of other cartridges that I have work normally on this console.

Share this post


Link to post
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

Loading...

  • Recently Browsing   0 members

    No registered users viewing this page.

×
×
  • Create New...