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Geneve Clock Chip MM58274 source?

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2 hours ago, mizapf said:


Preventing direct access to hardware is one of the reasons why the privileged mode was invented for processors. This could be done on the TMS99105 since it has such a mode. You cannot restrict the address access, but you could use a CRU bit to guard the clock hardware, and the TMS99105 allows access to CRU addresses 1C00 and higher only in privileged mode.

Yes, but it's still tricky to apply the tools to the problem at hand. Like you said, 99105 does not have "protected memory" features (The TM 990s with map feature with LMF instruction sort of do.)


I am going to place all of MDOS in user mode. (So the supervisor is invoked anytime MDOS does an XOP or there is an interrupt.) 


But it's MDOS itself reading and writing the clock. For instance to implement the DATE command, the XOPs for get/set date time, etc.


To present a hardware abstraction layer, the memory mapper (in the FPGA) would have to act when it sees certain addresses in certain modes.


I could do that... I've thought it all through. Some ways are:


1. Implement page faulting for certain mode bits+addresses. Raise INT2 for page fault. Handle faults in software. Really gross--essentially you have to decode the offending instruction to implement it.


2. Put a big ball of FPGA glue on those addresses, which synthesizes the expected read/write behavior at F130-F14F ports. If I'm doing that, I might as well use any clock chip behind the glue. 


3. I would prefer to use real chips, and just attach the MM58174 clock chip to the expected memory-mapped ports. These would be F130-F13F when MDOS mode is active.

The FPGA would barely get involved. It just  outputs the page register value to the bus like any other memory cycle. 


So my need is still to understand in detail what those clock memory-mapped ports are in MDOS mode. Why they seem to be read at F130-F13E but written at F130-F14E. And why I see MDOS write F13E as both the clock settings register CKSTRG and a data register.



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