Jump to content

Bringing up "Geneve 2020": Debugging Help Please!

Recommended Posts

53 minutes ago, dhe said:

That is a short version of the one I recall reading. It's all in there somewhere.


Ah, here's the bigger one I remember.



I must be thinking of the TILINE interface, which allows for memory transfers both ways between CPUs.

  • Like 1

Share this post

Link to post
Share on other sites

I don't remember all details; it's many years ago that I wrote the emulation.


(Just had a short look in the specs...)


In general, there are status bits that indicate the completion of a command and the kind of completion (success, failure). You can also set an interrupt for the completion of a command. I'd have to look into the HFDC DSR to check which way it is working.

  • Like 2

Share this post

Link to post
Share on other sites

I think the only place I really remembering DMA work was in the copy command of MDOS. MDOS would check ram free and cut loose DMA Transfer of the files directly into ram - as much as was available - did really phenomenal things with disk copies - suck it all in, spew it all out!  The copy code for MDOS is rather lengthy....

  • Like 1

Share this post

Link to post
Share on other sites

It might be the RAM is not working. I have a bigger test program that does a CRU operation early on.


I see the bus state is B, which is UI cycle.  I see that the red trace, ALATCH, skips a beat . That is, the CPU adds a wait state, which it does for all CRU instructions. 



If I go back a little way, I see the CPU has fetched an instruction from 0018. It writes to 8018, which is R12, then reads from 8018.

Presumably the read from 8018 is the SBZ executing and computing the address.



Here is the list file:

0018 0018 020C  20  li   r12,lights
     001A 2200     
0019 001C 1E00  20  sbz  0              led

Unfortunately, the address bus in the CRU cycle shows FFFF. Maybe the RAM is not working. (sbz should produce the address 2201. the last bit of addr is MEM which is 1. I didn't display the CRU output bit of 0 here.)


Something else is not working. The IO state is supposed to cause the bus signal:


Address   Signal

0000-7FFE SERENA*   serial CRU enable

8000-FFFE PARENA*   parallel CRU enable


I see neither one. 




Reviewing the schematic.. PARENA* is broken in a dumb way.

SERENA* would not activate if address is 8000 or up.

I bet that if I troubleshoot the RAM, then I will get SERENA* . but parallel CRU is broken on this version of the CPU card.

I didn't look at the RAM as much as the ROM yesterday.


  • Like 1

Share this post

Link to post
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.

Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.


  • Recently Browsing   0 members

    No registered users viewing this page.

  • Create New...