1050 troubleshooting

[cwilbar]

 

I recently aquirred another 1050.  This one has a genuine Happy enhancement in it. 

 

Initially it did not turn the drive spindle.

 

I tested another PCB in the 1050 and everything worked.  So, issue is on the PCB.

 

I tested the Happy enhancement on the spare PCB, works great.

 

I then noticed that all the 47uF caps had leaked causing corrosion.  I removed all the parts that had corrosion, cleaned up the PCB, tinned the pads, re-used components that were fine, replaced one broken resistor and found a broken trace (for the ground side of the drive motor !).

 

Now it spins the disk, tracks the head (though the tracking sounds 'rough' where with my spare board it sounds smooth, though on both boards it appears to be tracking out and back to track zero).

 

I tried swapping the FDC and RIOT, no change.

 

However, disks will not read.  I'm studying the schematic to figure out the best points to trace the signal from the read head through to the FDC.

 

Anyone seen a failure in the circuitry between the heads and the FDC ?  (I'm guessing the issue is there, but that may not be so).

 

 

[TGB1718]

You probably have, but did you clean the head.

 

Again, you probably have these, but just in case, they show the TP's to check and

the board layout where they physically are

 

Edited October 28, 2020 by TGB1718
added diagrams

[+Nezgar]

Have you tried swapping the mech itself into the working drive? To confirm if the mech itself is good.

 

Careful to make sure the WDC controller goes back with the original PCB, as each 1050 motherboard is calibrated to each chip... may cause read/write reliability issues otherwise, especially in MFM modes (enhanced/double density)

[cwilbar]

Yes, mech is good.  I took my spare 1050 PCB w/Tandon firmware (this is a Tandon mech) and tested the mech.  I've tested the Happy enhancement on this spare PCB with the mech, and all good.

 

The issue is on the 1050 PCB.  I'm suspecting a failure between the read head and the FDC, but if there is any post processing before shipping off to the SIO, could be logic in there too.  Figured it would be easiest to trace the signal from the head through to the FDC to confirm/reject the theory that it is somewhere in there.