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SGS Thompson TS68483 user manual ?

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A really really remote chance, does anybody have the user manual for a SGS Thompson TS68483 graphics chip.

I have the 30 page datasheet and the similar section from the Graphic Processors Data Book Mar89

They both refer to a TS68483 user manual  but i've spent many hours on the net trying to find it.

 

I decided to use the TS68483 on my TMS99105 system video card as it seemed to be one of the oldest chips that could still do 640x480 VGA, it wasn't designed to but it will.

I have it running just using the datasheet but i am having an issue with corruption just during data transfer to/from the viewport, all other functions work fine.

I think it's just an issue with the exact loading sequence of the FIFO but the datasheet is no help apart from saying what the registers are.

I know i could have used something with more info around but then i would have just been copying somebody else's design.

 

Many thanks,

 

Jim

 

TS68483 video card.jpg

Edited by Jimhearne
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4 hours ago, Jimhearne said:

A really really remote chance, does anybody have the user manual for a SGS Thompson TS68483 graphics chip.

I have the 30 page datasheet and the similar section from the Graphic Processors Data Book Mar89

They both refer to a TS68483 user manual  but i've spent many hours on the net trying to find it.

 

I decided to use the TS68483 on my TMS99105 system video card as it seemed to be one of the oldest chips that could still do 640x480 VGA, it wasn't designed to but it will.

I have it running just using the datasheet but i am having an issue with corruption just during data transfer to/from the viewport, all other functions work fine.

I think it's just an issue with the exact loading sequence of the FIFO but the datasheet is no help apart from saying what the registers are.

I know i could have used something with more info around but then i would have just been copying somebody else's design.

 

Many thanks,

 

Jim

 

TS68483 video card.jpg

I really enjoyed learning about this graphics chip. I only  found the datasheet (30 pages) and databook (same, in 40 pages starting on 171). Those were on bitsavers.org under both Thomson and STMicroelectronics (but SGS folder is older stuff.)

 

Is that a bus with DIN-41612? Did you use the 64 or 96 pin? It looks like a 160x100 Eurocard single.

 

I'm building my 99105-Geneve 2020 using the 96 pin, on the Retrobrewcompting.org ECB backplane.

 

 

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Hi, yes, that's the same 2 datasheets i have, they are essentially the same just with different formatting.

The TS68483 seems fairly available s/h but there don't seem to have been any big users of it.

I found a very high end VME bus video card using it plus a couple of industrial applications where it just drives an graphics EL display.

I couldn't track down the source code for any of them though, that might have shed some light on the correct viewport access.

 

The card is a DIN-41612 single eurocard, i'm using the 96 way a+c connectors, so 64 pins with the middle row missing.

This is the 3rd card I've made for my system, the bus is TI's E-Bus which i already had some other cpu cards for.

 

I have a Powertran Cortex which has an E-Bus expansion socket on it, that lead onto E-Bus cards and then the TMS99105 cpu which didn't seem to have been used much, so i thought i'd make my own system around it.

 

The processor board has the TMS99105 running at 24mhz clock, 32K words of EEPROM, 512K of paged RAM and a TMS9902 with TTL outputs (connected to a TTL serial to USB lead), at the moment it's running Stuarts port of the Powertran Cortex Basic & EVMBUG

The I/O card has floppy, IDE, RTC, another serial port (with true 232 output levels), a parallel port via a TMS9901, a RTC , and a PIC micro (we won't talk about that, change of plans).

The video card has 512K words of static video Ram and a 18 bit RAMDAC, at the moment it does 640x480 x 16 colours using the shift registers internal to the TS68483, it can do 256 colours with external shift registers, thats what the second CPLD on that board is for, i've not done that yet, i want to get the 16 colours working fully first.

The video card also has connections for a PS2 keyboard and mouse which i hope to interface via the first CPLD since it's only doing address decoding and an I/O port at the moment.

On all the boards the I/O connections are just via PC pinout headers.

There is also a passive motherboard with termination resistors at each end as per the E-Bus spec, and i've got some prototyping cards which are essentially just the buffers and CPLD from the I/O card with the rest of the pcb as a prototyping area.

 

The Altera CPLD's are just replacing a lot of discrete TTL, the only way really of getting the boards on single Eurocards.

The CPLD's also suit my way of working, much more hands on than sitting down and designing it all first. 

If i want to try different ideas in the logic i just reprogram the CPLD, no soldering iron required.

 

Sorry, waffling on too much,

 

Jim

 

 

IO card-s.jpg

cpu board-s.jpg

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I came up with the same two documents you did. There doesn't seem to be a lot of data on it online. . .

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On 2/12/2021 at 4:43 PM, Jimhearne said:

Hi, yes, that's the same 2 datasheets i have, they are essentially the same just with different formatting.

The TS68483 seems fairly available s/h but there don't seem to have been any big users of it.

I found a very high end VME bus video card using it plus a couple of industrial applications where it just drives an graphics EL display.

I couldn't track down the source code for any of them though, that might have shed some light on the correct viewport access.

 

The card is a DIN-41612 single eurocard, i'm using the 96 way a+c connectors, so 64 pins with the middle row missing.

This is the 3rd card I've made for my system, the bus is TI's E-Bus which i already had some other cpu cards for.

 

I have a Powertran Cortex which has an E-Bus expansion socket on it, that lead onto E-Bus cards and then the TMS99105 cpu which didn't seem to have been used much, so i thought i'd make my own system around it.

 

The processor board has the TMS99105 running at 24mhz clock, 32K words of EEPROM, 512K of paged RAM and a TMS9902 with TTL outputs (connected to a TTL serial to USB lead), at the moment it's running Stuarts port of the Powertran Cortex Basic & EVMBUG

The I/O card has floppy, IDE, RTC, another serial port (with true 232 output levels), a parallel port via a TMS9901, a RTC , and a PIC micro (we won't talk about that, change of plans).

The video card has 512K words of static video Ram and a 18 bit RAMDAC, at the moment it does 640x480 x 16 colours using the shift registers internal to the TS68483, it can do 256 colours with external shift registers, thats what the second CPLD on that board is for, i've not done that yet, i want to get the 16 colours working fully first.

The video card also has connections for a PS2 keyboard and mouse which i hope to interface via the first CPLD since it's only doing address decoding and an I/O port at the moment.

On all the boards the I/O connections are just via PC pinout headers.

There is also a passive motherboard with termination resistors at each end as per the E-Bus spec, and i've got some prototyping cards which are essentially just the buffers and CPLD from the I/O card with the rest of the pcb as a prototyping area.

 

The Altera CPLD's are just replacing a lot of discrete TTL, the only way really of getting the boards on single Eurocards.

The CPLD's also suit my way of working, much more hands on than sitting down and designing it all first. 

If i want to try different ideas in the logic i just reprogram the CPLD, no soldering iron required.

 

Sorry, waffling on too much,

 

Jim

Not waffling at all--it's very interesting to me.

 

I just read about the E-Bus at http://www.powertrancortex.com/hardware/Cortex_1985-09_(Sep).pdf

I don't know much about Cortex.

 

Because I was acquainted with N8VM, I used their ECB bus. It's not lovely, since it evolved from Z80 to 8086 and 68020. The 99105 is most similar to the 8086, so I can rest on top of  that. Parallel CRU of the 99105 in 00-FF asserts IORQ. The B row of the DIN-41612 has been defined at retrobrewcomputing to provide +8 bits of databus, extended address space, and 8 bits of interrupt code. 

 

I'm allowing myself to use SMT in 1.27mm (half the 0.1" TH) I tend to use one 22V10 SPLD per board to knock out 4 TTL chips or so. With that, my first 99105 CPU card fit on a half-Eurocard. So far, I haven't exceeded a 100x100 size, which is the cheapest to get made. Of course, to look nice, it will have to consolidate onto single EuroCard 100x160.

 

I like your video solution. I'm going a different direction with mine, starting with V9958 for compatibility.

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On 2/12/2021 at 5:43 PM, Jimhearne said:

The processor board has the TMS99105 running at 24mhz clock, 32K words of EEPROM, 512K of paged RAM and a TMS9902 with TTL outputs (connected to a TTL serial to USB lead), at the moment it's running Stuarts port of the Powertran Cortex Basic & EVMBUG

...

The Altera CPLD's are just replacing a lot of discrete TTL, the only way really of getting the boards on single Eurocards.

 

cpu board-s.jpg

 

Do you mind if I butt in and ask a question about your processor board design, because I am toying with the idea of designing/building a 99105 SBC myself?

 

Are you using the Altera MAX7000 (EPM7160S) to both directly latch the address, and also provide the paged-memory-mapping at the same time?  If I am understanding "The 99000 Microprocessor" book (and the data sheets), that seems to be the only way that I can imagine you using 70ns SRAM and still being able to run at a full 6MHz external clock rate with no wait-states.

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Posted (edited)

On my 99105 board, I didn’t make timing on 70ns SRAM. I have a latch and bus driver for the address pins. There are Als245’s in the cpu and the memory card, which uses one more 138 for decoding. 
 

Im running at 3mhz until I get my rev2 bios card in 2 more weeks. The bios card is where I put the EEPROM and SRAM as well as bank switching. This memory is used in privileged  mode (PSEL unless long distance is in effect.)

 

I do chip select and bank number in a 22V10-10ns SPLD. but there’s also a 157 stage to turn banking off.

 

. So I’ve got a lot of chips in the memory path. 

 

I’m getting timing at 6mhz fixed by using 45ns flash ROM (SST39F010) and 10ns static ram (ISSI 128k x 16 in SOJ-44)

 

actually my EEPROM 70 NS was working at 6mhz but not my 70ns SRSM. 

 

I am still debugging my 9902 on wire wrap protoboard.
 

I scored 3 Vector wire-wrap 41612 male connectors on eBay, but I haven’t used them yet. I’ve still got my proto using  a 2x32 and 1x32 long pin headers. from peconnectors.com , love that place , and their 41612 parts are pretty nice and affordable. They go thru the 3.2 mm backplane alright.  

 

 

 


 

 

Edited by FarmerPotato
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Posted (edited)
13 hours ago, elmer said:

 

Do you mind if I butt in and ask a question about your processor board design, because I am toying with the idea of designing/building a 99105 SBC myself?

 

Are you using the Altera MAX7000 (EPM7160S) to both directly latch the address, and also provide the paged-memory-mapping at the same time?  If I am understanding "The 99000 Microprocessor" book (and the data sheets), that seems to be the only way that I can imagine you using 70ns SRAM and still being able to run at a full 6MHz external clock rate with no wait-states.

 

Hi, the 16 bit processor bus is demuliplexed with a pair of 74ALS573 transparent latches (like the 74LS373 but with a nicer pin layout) and feed directly to the RAM and EEPROM.

The CPLD also demultiplexes the processor bus internally (to save CPLD pins) and outputs the chip select signals for the RAM and EEPROM and the also the upper address lines for paging the RAM

 

I'm not a great one for sitting down and looking at timing diagrams, and it was a long time ( around 5 years) since i designed the processor board, so i can't say for certain I'm not exceeding the specs for the RAM but it seems to work.

I did have to add one wait state for the EEPROMS at 6mhz clock but then they are 150ns parts so not really surprising.

Eventually the EEPROM code will be copied into RAM at boot time and then the EEPROM disabled so the wait states on that don't really matter.

 

I've attached the last schematic i have on the computer but i think i marked up a couple of changes on my printed copy.

 

Jim

 

BTW, the board is 4 layers, the ground and power planes aren't shown on the PCB in the attachement.

 

 

 

 

 

 

TMS991xx Iss2a schematic and pcb.pdf

Edited by Jimhearne
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18 hours ago, FarmerPotato said:

On my 99105 board, I didn’t make timing on 70ns SRAM. I have a latch and bus driver for the address pins. There are Als245’s in the cpu and the memory card, which uses one more 138 for decoding. 
 

Im running at 3mhz until I get my rev2 bios card in 2 more weeks. The bios card is where I put the EEPROM and SRAM as well as bank switching. This memory is used in privileged  mode (PSEL unless long distance is in effect.)

 

I do chip select and bank number in a 22V10-10ns SPLD. but there’s also a 157 stage to turn banking off.

 

. So I’ve got a lot of chips in the memory path. 

 

I’m getting timing at 6mhz fixed by using 45ns flash ROM (SST39F010) and 10ns static ram (ISSI 128k x 16 in SOJ-44)

 

 

 

Yes, it sounds like you do have a lot of chips in your memory path! ;)

 

That's where (I hope), a CPLD could help, especially Atmel's still-in-production ATF1508, which offers a few extra tricks over the older Altera EPM7128S, despite being basically compatible.

 

IIRC, with the 22V10 you only have 10 flip-flops for a bank register ... may I ask how you've layed out your memory mapping within the CPU's 64KB?

 

 

8 hours ago, Jimhearne said:

Hi, the 16 bit processor bus is demuliplexed with a pair of 74ALS573 transparent latches (like the 74LS373 but with a nicer pin layout) and feed directly to the RAM and EEPROM.

The CPLD also demultiplexes the processor bus internally (to save CPLD pins) and outputs the chip select signals for the RAM and EEPROM and the also the upper address lines for paging the RAM

 

I'm not a great one for sitting down and looking at timing diagrams, and it was a long time ( around 5 years) since i designed the processor board, so i can't say for certain I'm not exceeding the specs for the RAM but it seems to work.

 

Ah, OK, so you are using multiple address latches, but mainly to save pins on the CPLD, and not because it just couldn't actually handle all the latching.

 

And you're using some of the CPLDs flip-flops to create mapping registers for memory paging. Did you decide to use 4 pages of 16KB, or 8 pages of 8KB ... or am I wrong, and you picked a different scheme?

 

 

 

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51 minutes ago, elmer said:

 

Yes, it sounds like you do have a lot of chips in your memory path! ;)

 

That's where (I hope), a CPLD could help, especially Atmel's still-in-production ATF1508, which offers a few extra tricks over the older Altera EPM7128S, despite being basically compatible.

 

IIRC, with the 22V10 you only have 10 flip-flops for a bank register ... may I ask how you've layed out your memory mapping within the CPU's 64KB?

Yes, my 22V10 registers are 3 bits for ROM bank, 4 for RAM bank. 

0000 ROM Page 0

4000 ROM banking 0-7

8000 RAM Page 0

C000 RAM banking 0-15

 

Interrupts should not depend on or change bank numbers.

 

The ROM/RAM is enabled for PSEL memory access or for Macrostore access. (I unify Macrostore ROM with the system ROM)

So the CPLD takes inputs PSEL,MEM,BST1,BST2 to produce MEMSEL. 

A13 goes to the 157 multiplexer enable. A14 goes to the 157 switch.

 

The 157 puts either the ROM or RAM bank# onto the upper address lines (A14=0 or 1), or all 0s (A13=0).

This lets me wire the 4 memory chips address lines together (2 EEPROM, 2 SRAM, in 32-pin DIP)

 

If I need to cram more in, I'll move up to the ATF1508. In particular I think the 750 or 1500 series can have buried flip-flops going to combinatorial outputs? 

 

User memory is totally different. I haven't started that yet but there will be up to 32MB of 4K paged DRAM. Definitely an FPGA for the memory mapper (LS610 doesn't fit the Geneve scheme where one word holds two bank registers.)

 

 

 

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2 hours ago, elmer said:

 

Ah, OK, so you are using multiple address latches, but mainly to save pins on the CPLD, and not because it just couldn't actually handle all the latching.

 

And you're using some of the CPLDs flip-flops to create mapping registers for memory paging. Did you decide to use 4 pages of 16KB, or 8 pages of 8KB ... or am I wrong, and you picked a different scheme?

 

 

No reason at all why the CPLD couldn't demultiplex the bus for the ROM / RAM apart from the fact it would need another 16 pins to output the demultiplexed Address bus.

And i needed the pins for other uses.

 

At the moment i have 2 types of mapping in the CPLD, i can make any 4K word block of the 32K word memory space be Read only EEPROM, Writeable EEPROM, RAM, or EEROM on Read and Ram on Write.

The last of those modes is for fast copying of ROM into RAM.

 

I also have paging of any 8K or 16K memory block from the remainder of the 512K word of RAM into the main memory map, pretty much a copy of how the 74LS612 does it.

The size of the actual blocks isn't determined yet as it will probably be determined by how much else i have in the CPLD

 

I've already upgraded from the EPM7128S to the EPM7160S and then the  EPM7192S (all pin compatible except the 7128 has 4 more I/O pins) and now i'm using a EPM71256A which is a 3.3V version but has 5 volt compatible I/O, that's a flat pack device on a daughter board (with 3.3V regs) which breaks it out to a pin arrangement to match the CPLD PLCC socket on my main board.

The number on these CPLD's is the number of Macrocells , and i quickly found out that each latch uses a macrocell and having lots of latches for creating the memory mapper etc uses a lot of macrocells.

Hence why i kept upgrading the CPLD.  

The latest upgrade was prompted by trying to add a DMA controller into the CPLD, which of course needs more counters and latches.

Unfortunately I'm now running up against issues where the Altera software can't fit everything into the CPLD, not because the aren't enough macro cells but simply because it can't Fit all the interconnections.

I have to do more research on the advanced options in the Altera software.

Also, i recently found out there is a EPM8000 series which run off 5 V and appear to offer still more macrocells and improved routing. 

Unfortunately they aren't pin compatible with the EPM7000 series so another daughter board coming up.

 

Jim

 

 

 

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On 4/17/2021 at 3:24 PM, FarmerPotato said:

Yes, my 22V10 registers are 3 bits for ROM bank, 4 for RAM bank. 

0000 ROM Page 0

4000 ROM banking 0-7

8000 RAM Page 0

C000 RAM banking 0-15

 

The ROM/RAM is enabled for PSEL memory access or for Macrostore access. (I unify Macrostore ROM with the system ROM)

So the CPLD takes inputs PSEL,MEM,BST1,BST2 to produce MEMSEL. 

...

User memory is totally different. I haven't started that yet but there will be up to 32MB of 4K paged DRAM. Definitely an FPGA for the memory mapper (LS610 doesn't fit the Geneve scheme where one word holds two bank registers.)

 

On 4/17/2021 at 5:48 PM, Jimhearne said:

At the moment i have 2 types of mapping in the CPLD, i can make any 4K word block of the 32K word memory space be Read only EEPROM, Writeable EEPROM, RAM, or EEROM on Read and Ram on Write.

The last of those modes is for fast copying of ROM into RAM.

 

I also have paging of any 8K or 16K memory block from the remainder of the 512K word of RAM into the main memory map, pretty much a copy of how the 74LS612 does it.

 

Thank you gentlemen! :)

 

It is very interesting to hear your different schemes and designs for partitioning memory, and I suspect that you are both creating systems that are far more ambitious and complex than I would attempt.

 

 

FarmerPotato: As far as the EPM7xxx and ATF15xx series chips, yes both offer buried flip-flops. It is definitely one of the big advantages in going for a CPLD that offers more capability than the 22V10 or 16V8. You might find that the 44-pin PLCC packaged of the 1504 offer you a decent compromise beween board-space usage and added capabilities.

 

 

Jimhearne: Hahaha ... you're really going through a lot of different CPLD chips there! I can't find any mention of an EPM8000 series of chips, perhaps you mean the old 5V FLEX 8000 series of FPGAs?  You'll definitely get more capability, but then you will also have to deal with adding a chip to hold the FPGA's configuration bitstream, and possibly some new development hardware so that you can write the bitstream to that chip.

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Ah, yes, the chip i was thinking of was the Flex 8000 series , i'd not looked at it closely yet.

The Datasheet refers to it as a CPLD still but as you say, it's configuration needs to be loaded from an external device, it's not got internal EEPROM.

 

That's probably a step too far for my design.

My design "rules"  are just to use the CPLD to replace discrete chips and therefore require a smaller pcb.

If i wanted to i could design the entire system on a modern FPGA or even emulate it on a PC, but that's not what is fun for me, i like making like designing using the old parts, getting them working and laying out PCB's.

I may end up with a daughterboard on the CPU card so i can use a real TMS9911 DMA controller and a 74LS612 memory mapper, they are the 2 things that take up all the latches in the CPLD.

 

I think one big difference between FarmerPotato and my design is that he is trying to keep his compatible with the TI99/4A and Geneve,  and i started from the ground up with no past experience of these machines.

My interest in TI systems came from always wanting a Powertran Cortex when they came out (but not being able to afford it), and about 10 years ago managing to acquire a unbuilt kit for one.

Then meeting Stuart and his TMS99120 board which then lead onto me finding out more about TMS99xxx series of CPU's and deciding to built my own system around one.

It's a bit different as everybody uses the 6502, Z80 etc etc for Retro computers.

And when the E-Bus handbook turned up I decided to use the E-BUS standard as TI did cards up to the TMS9995 cpu,  so a TMS99xxx card would have been their next step I'm sure.

 

Jim

 

 

 

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7 hours ago, Jimhearne said:

My design "rules"  are just to use the CPLD to replace discrete chips and therefore require a smaller pcb.

 

If i wanted to i could design the entire system on a modern FPGA or even emulate it on a PC, but that's not what is fun for me, i like making like designing using the old parts, getting them working and laying out PCB's.

 

I may end up with a daughterboard on the CPU card so i can use a real TMS9911 DMA controller and a 74LS612 memory mapper, they are the 2 things that take up all the latches in the CPLD.

 

I completely agree with the joy of using old parts at the heart of the system (especially the CPU), and keeping the modern stuff as convenient replacements for logic and memory chips.

 

Another thing that I think of as fair, is replacing old-and-cantankerous serial port hardware with something modern like an FT245RL, which gives you essentially the same functionality, but is much easier to use.


From what I can see, the first challenge with trying to design a simple system using the TMS99105, is going to be running a no wait-state memory cycle, with only 85ns from ALATCH-hi to needing to having the data available at the CPU's pins.

 

That isn't too bad if you're willing to buy/solder a 25ns-or-less SOP/TSOP package chip onto your circuit board, but it seems a bit more challenging if you're looking at the modern SMT PCB prototyping companies, who seem to be more likely to only offer 55ns 5V SRAM parts.

 

Then again, *if* you can design for the 55ns memory speed, you can take advantage of the wide availability of dirt-cheap 55ns SST39SF040 flash ROM parts. ;)

 

If I am understanding the datasheets correctly, then the 74LS612 is going to need some really fast SRAM to reliably run the TMS99105 with no wait-states.  Its tAVQV1 time of 39-79ns would seem to push the limits of your timing, especially with 74ALS573 buffers between it and the CPU, with 3-18ns delays on both the address and data. If you then add in any more decoding logic between the 74LS612 and the ROM/RAM, or any card-to-card buffering, then things would seem to get pretty dicey.

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4 hours ago, elmer said:

From what I can see, the first challenge with trying to design a simple system using the TMS99105, is going to be running a no wait-state memory cycle, with only 85ns from ALATCH-hi to needing to having the data available at the CPU's pins.

 

That isn't too bad if you're willing to buy/solder a 25ns-or-less SOP/TSOP package chip onto your circuit board, but it seems a bit more challenging if you're looking at the modern SMT PCB prototyping companies, who seem to be more likely to only offer 55ns 5V SRAM parts.

 

Then again, *if* you can design for the 55ns memory speed, you can take advantage of the wide availability of dirt-cheap 55ns SST39SF040 flash ROM parts. ;)

I'm going for no wait-states at 6MHz, but today I've only reached 3MHz.

I used TMS27C010-70 EEPROM and Toshiba TC551001BPL-70 SRAM.

 

In my simplified wire-wrap board, I saw my TMS27C010-70 EEPROM meet timing at 6MHz. That was with TMS99105 to '645 to TMS27C010. With a ALS138 decoding the ROM or RAM CE. I call this the BIOS memory card because it contains supervisor-mode and macrostore code.

 

(Oh yeah, I've separated address and data lines on the backplane. The CPU card drives addresses with ALS573 and data bus/control with ALS645. Cards can latch the address off the data bus if they want to, e.g. to save pins on an FPGA.)

 

However, my SRAM, Toshiba TC551001BPL-70, did not meet  timing. Probably the EEPROM was more better than 70ns. And I still expect more logic on the BIOS memory card (buffers, bank decode in 22V10, '153 multiplexer). At least the 22V10 is very fast (5-10ns).

 

Stuart used W24257-70 RAM (32K x 8 ) and those met timing apparently.

 

I'm not sure what the fanout line drive capability of the '573 and '645 are. I'm unsure which cards will need another line driver chip, or if they can load the bus directly.

 

 

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Posted (edited)
2 hours ago, FarmerPotato said:

However, my SRAM, Toshiba TC551001BPL-70, did not meet  timing. Probably the EEPROM was more better than 70ns. And I still expect more logic on the BIOS memory card (buffers, bank decode in 22V10, '153 multiplexer). At least the 22V10 is very fast (5-10ns).

 

Stuart used W24257-70 RAM (32K x 8 ) and those met timing apparently.

 

If you're following Start's example of driving the EPROM and SRAM chips' /OE lines with the CPU's /RD signal, then that might be where your  problem is.

 

Taking a look at the TC551001BPL-70's datasheet, it says that the /OE Access Time is 35ns, the same as the 55ns SRAM that I can get.

 

Add another (generous) 7ns for the signals to propagate throught the 74ALS645, and you've got 42ns before the CPU can see the valid data.

 

According to the TMS99105 data sheet, the time between /RD and when the CPU expects the data to be valid, is Tded = ((1/2 Tc2) - 63) = (83 - 63) = 20ns.

 

 

If you look carefully again at Stuart's website, it says that he used a W24257AK-20, with a /OE Access time of 10ns ... which does meet the TMS99105's timing requirements.

 

<EDIT>

 

This timing condition is probably why some of the examples in The 99000 Microprocessor book seem to suggest only using the /RD signal to activate the 74ALS573 / 74ASL645 data buffers, and not the memory chips' /OE signals.

Edited by elmer

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On 4/20/2021 at 4:12 AM, Jimhearne said:

I think one big difference between FarmerPotato and my design is that he is trying to keep his compatible with the TI99/4A and Geneve,  and i started from the ground up with no past experience of these machines.

 

My interest in TI systems came from always wanting a Powertran Cortex when they came out (but not being able to afford it), and about 10 years ago managing to acquire a unbuilt kit for one.

 

Your experience is similar to mine, in that I have no past history with the TI99/4A or Geneve, and have no paticular interest in keeping  compatibility with them.

 

I remember seeing the Cortex issues of ETI in W.H.Smiths, avidly reading the details, and then lusting after the machine, even though I couldn't afford it.

 

Somehow I got hold of a TMS9995 Data Manual, and I was absolutely fascinated by the architecture. Then I became even more fascinated when I read the TMS99105/TMS99110 Data Manual.

 

But alas, I had neither the spare cash, nor the electronic skills at the time, and the fascination never led to any action. :(


Now that SMT Prototyping services are becoming affordable, it is fun to think of how a Cortex successor might be designed, especially since Matthew Hagerty's amazing work on the F18A-MK2 would seem to provide an excellent solution to the otherwise difficult video portion of such a machine.

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On 2/12/2021 at 5:43 PM, Jimhearne said:

The processor board has the TMS99105 running at 24mhz clock, 32K words of EEPROM, 512K of paged RAM and a TMS9902 with TTL outputs (connected to a TTL serial to USB lead), at the moment it's running Stuarts port of the Powertran Cortex Basic & EVMBUG

The I/O card has floppy, IDE, RTC, another serial port (with true 232 output levels), a parallel port via a TMS9901, a RTC , and a PIC micro (we won't talk about that, change of plans).

 

I have another question for you ...

 

It looks to me like just dividing the TMS99105's 6MHz clock by two to generate a 3MHz clock for the TMS9901 and TMS9902 *might* be enough to interface both chips to the TMS99105 without any extra logic, and without needing to buy the faster TMS9901NL-40.

 

Is that what you found with your board, or did you have to add an extra wait-state to each TMS9901 and TMS9902 access (beyond the 1 automatic wait-state that is part of the TMS99105's LDCR and STCR instructions)?

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Yes, dividing the TMS99105 clkout by 2 (done in the CPLD) to give 3mhz seems to work fine as a clock for the TMS9901 / 2 without any additional wait states.

In my understanding, the CRU access and the clock input to the TMS9901 / 2 are somewhat independent, the clock input on them is just for the internal timers & shift registers, it's not even clear if it has to be synchronised to the cpu clock, certainly the phase of the clock compared to the CPU clock doesn't seem to matter as i tried both polarities.

I've also run the TMS9902 clock at 4 and even 6 mhz, all of my parts seem to work at at 4mhz and most at 6mhz, both -4 and non -4 parts.

But i've left it at 3mhz for the moment.

 

Jim

 

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4 hours ago, Jimhearne said:

Yes, dividing the TMS99105 clkout by 2 (done in the CPLD) to give 3mhz seems to work fine as a clock for the TMS9901 / 2 without any additional wait states.

 

Thanks!

 

It certainly looked like the 99105 was deliberately designed to allow the use of the old 3MHz CRU chips, but it's wonderful to have that confirmed.

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