Reading VDP Write-Only Registers

[charlietunaz]

I'm in the process of learning assembly language, so please be gentle with the responses

I was looking at the editor/assembler book and another introductory book on assembly language, and they both indicate the following about VDP write-only registers:

VDP Register 1:

Default Value E0, which in binary = 1110 0000

Bit 0 = 4/16k Selection

Bit 1 = Blank Enable Disable

Bit 2 = Interrupt Enable/Disable

Bit 3 = Text Mode

Bit 4 = Multicolor

Bit 5 = Reserved, default value = 0

Bit 6 = Sprite Size

Bit 7 = Sprite Magnification

 

I'm used to read bits like this

7 6 5 4 3 2 1 0

1 1 1 0 0 0 0 0

 

Therefore, for me, this means that the default value E0 indicates:

Sprite magnification, Size, and the reserved bit are all on which does not make sense

 

However, reading it like this,

 

0 1 2 3 4 5 6 7

1 1 1 0 0 0 0 0

 

Indicates:

16K RAM operation, display is allowed, Interrupts Enabled, which actually make sense, 

but I always thought 

Bit 0 = 0,1

Bit 1 = 2

Bit 2 = 4

Bit 3 = 8

Bit 4 = 16

Bit 5 = 32

Bit 6= 64

and

Bit 7 = 128

 

So it is confusing, seeing E0 from left to right 1110 0000

and looking at this example as 0000 0111

 

Am I reading bits differently from how you read in 6502?  or have I been reading bit values wrong all this time?  Please clarify this confusion!

 

 

 

[brain]

I can't say for sure, but I think TI notated things that way on the 99/4a.  FOr instance, the addresses are A0-A15, where A15 is the LSB.  I'd expect the data lines to be the same

[+Lee Stewart]

TI refers to the bits in a byte or word from left to right as bit0 – bit7 or bit0 – bit15. And, you read them that way, i.e., you do not invert the order to make sense of them. Your example is E0 (1110 0000) and bit0 is the MSb (Most Significant bit).

 

...lee

[HOME AUTOMATION]

machine instruction example...

 

>7000 JMP >7000 

 

assembles as   OPCODE >1000

 

 

Stored at >7000...

 

>7000 10

>7001 00

 

...MSB is  stored at the lower of the two addresses.

 

 

Endianness (WIKIPEDIA)

 

So, this system uses BIG ENDIAN.

 

[charlietunaz]

28 minutes ago, HOME AUTOMATION said:

machine instruction example...

 

>7000 JMP >7000 

 

assembles as   OPCODE >1000

 

 

Stored at >7000...

 

>7000 10

>7001 00

 

...MSB is  stored at the lower of the two addresses.

 

 

Endianness (WIKIPEDIA)

 

So, this system uses BIG ENDIAN.

 

Amazing what you learn every day.  It's going to take me a little longer to adapt to this system but at least I know I am not going crazy.  Thanks for the explanation.

[HOME AUTOMATION]

44 minutes ago, charlietunaz said:

Amazing what you learn every day.  It's going to take me a little longer to adapt to this system but at least I know I am not going crazy.  Thanks for the explanation.

I suppose I would have similar issues on a 6502.

 

Although imperfect(because EASYBUG alters things in CPU RAM and VDP), a quick way to learn how some VDP write-only registers effect things, is to change their values using EASYBUG...

 

Although EASYBUG does not directly support writing to VDP registers. By simply accessing VDP addresses with the highest bit on, and the next three lower bits off(8), followed by the register # and desired byte value. The registers can be poked directly. This has proven useful in observing different color combinations, and changing mode bits somewhat.

 

In this example, I force EASYBUG into text-mode and run through color-combos, by simply pressing hyphen or enter.

 

   SUPERNOTES (link)

 

Try to excuse my facetiousness here ...sometimes I'm in my own place, a little too much!

Edited February 22, 2021 by HOME AUTOMATION

[matthew180]

This was an unfortunate era for TI, since they were numbering the bits in their bytes and words (16-bit backwards from the rest of the industry).  You can find internal memos where engineers complain about this, and TI did finally come around (not sure when, but I suspect they were not doing this for very long).  Sadly the TMS9900 CPU and 9918A VDP were caught up in the reverse bit numbering.  It is important, as other mentioned, to realize that is the *ONLY* the numbering that is reversed, and not the bit-values.  Bit-value goes up from right-to-left, just like they always have, and just like decimal numbers.  Basically this:

 

128 64 32 16  8  4  2  1  Bit *place value*, MSbit is always on the left

  0  1  2  3  4  5  6  7  TI bit *numbering* duing the 9918A era

  7  6  5  4  3  2  1  0  Bit numbering for the rest of the industry
------------------------
  1  1  1  0  0  0  0  0 = >E0

 

The MSbit is always on the left in both numbering schemes, and the "endian" of the 9900 CPU, while important to know when programming in assembly, has nothing to do with the bit numbering.

 

To help prevent errors, I find when working with the 9900 and 9918A that using the bit-value (or "weight") prevents ambiguity.  For example:

 

TI bit-2 would be bit >40 (0010 0000)

TI bit-5 would be bit >04 (0000 0100)

TI bits-2..4 would be bits >38 (0011 1000)

 

Specifying the bit positions this way works no matter how they are "numbered".

[ChildOfCv]

23 hours ago, charlietunaz said:

I'm in the process of learning assembly language, so please be gentle with the responses

Is the little baby gonna cry?  ?

23 hours ago, charlietunaz said:

I was looking at the editor/assembler book and another introductory book on assembly language, and they both indicate the following about VDP write-only registers:

VDP Register 1:

Default Value E0, which in binary = 1110 0000

Bit 0 = 4/16k Selection

Bit 1 = Blank Enable Disable

Bit 2 = Interrupt Enable/Disable

Bit 3 = Text Mode

Bit 4 = Multicolor

Bit 5 = Reserved, default value = 0

Bit 6 = Sprite Size

Bit 7 = Sprite Magnification

 

I'm used to read bits like this

7 6 5 4 3 2 1 0

1 1 1 0 0 0 0 0

Yeah, TI seemed to enjoy confusing us.  They show pins in the opposite order that you'd expect and also number bits that way.  Makes it hard to keep things straight when interfacing with other non-TI chips, or when constructing values in software.

 

TI seems to have sobered up eventually though.