# An article about the TMS9900

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What I mean by math error is that he's comparing cycles to cycles, without taking into consideration that the cycles occur at a 3 MHz rate in one device, but with a 12 MHz rate in the other.

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Yes, I just wanted to point out that this seems intentional to me, in order to calculate that ratio of instruction execution rate (MIPS) by input clock rate (MHz). As said, you can calculate a lot of ratios when the day is long.

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Yes, it may be intentional. But to make that correct you have to look at how many phases the clock cycle has too, since they don't do all these phases just because they like complexity. The actually perform something for each phase, so from that point of view, the TMS 9900 is a 12 MHz device too.

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5 hours ago, mizapf said:

Yes, I just wanted to point out that this seems intentional to me, in order to calculate that ratio of instruction execution rate (MIPS) by input clock rate (MHz). As said, you can calculate a lot of ratios when the day is long.

Yes, it may be intentional. But to make that correct you have to look at how many phases the clock cycle has too, since they don't do all these phases just because they like complexity. The actually perform something for each phase, so from that point of view, the TMS 9900 is a 12 MHz device too.

Thanks a lot for information.  However it seems I am rather baffled now.  My point is quite easy, according to official data the TMS9900 is at 3 MHz in the TI99/4A and the TMS9995 is at 12 MHz in the Geneve 9640.  Indeed the Geneve processor is much faster but it uses 4 times more clock cycles.  So if somebody wants to find out how fast are both processors at the same clock frequency he gets the obvious result that the TMS9900 is faster.  Maybe it is possible to think that the TM9900 actually uses 6 or 12 MHz in the TI99/4a, or the TMS9995 uses 3 MHz in the Geneve.  But I just took the numbers from open specs.  I added a comment in the pi-spigot result table "all official instruction timings use 1/4 of the CPU freq as the base, so ER may be regarded as 4 times less".  I added it because the matter is really complex for me.  However I have to confess that I prefer to think that the TMS9995 uses 12 MHz internally rather than just dividing it by 4...

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They take different clock inputs, but both run at the same internal frequency.

It is like a 486 DX2, only in reverse. A 486 DX2 66 takes a 33 MHz clock input and doubles it internally, but no one will argue it isn't a 66 MHz chip.

Similarly, the 9995 takes a 12 MHz input and divides it by four internally. We can only speculate as to why, but it clearly doesn't "run at" 12 MHz.

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Posted (edited)

Vol, have you read post #20 of

Edited by Stuart

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On 4/22/2021 at 9:01 PM, JB said:

Similarly, the 9995 takes a 12 MHz input and divides it by four internally. We can only speculate as to why, but it clearly doesn't "run at" 12 MHz.

We still don't have the proof for it.

On 4/22/2021 at 9:47 PM, Stuart said:

Vol, have you read post #20 of

Thank you for this link to interesting information.  I have corrected a bit my blog entry.

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1 hour ago, vol said:

We still don't have the proof for it.

The datasheet is clear that there's a 1/4 divider in the chip.

Granted, it does not explicitly say "and the processor runs at the divided clockerate", but they didn't include the divider for no reason(transistors cost money).

Empirical evidence shows that, with a 12 MHz input clock, the 9995 performs slightly better than a 9900 with a 3 MHz clock input, which is what is expected for a slightly improved 9900 running at 12/4 MHz. It is also what is expected for a much much worse version of the 9900 running at 12/1 MHz, but it is difficult to imagine how iterative updates could result in a 4x loss of performance.

I would say the onus is on you to prove the processor ISN'T clocked off of that divider, and it truly was included for no reason. And I look forward to your groundbreaking research in that regard.

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Extract from the TI Microsystems Designers Handbook, showing that the TMS9995 gives around twice the performance of the TMS9900, with the 9995 clocked from a 12 MHz crystal, and the 9900 with a 4-phase 3 MHz clock derived from a 12 MHz crystal.

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21 hours ago, Stuart said:

Extract from the TI Microsystems Designers Handbook, showing that the TMS9995 gives around twice the performance of the TMS9900, with the 9995 clocked from a 12 MHz crystal, and the 9900 with a 4-phase 3 MHz clock derived from a 12 MHz crystal.

Thank you very much for the so interesting table!  It is also very interesting for me what is the difference between the first two items?  What do these PROM/EPROM mean?

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1 hour ago, vol said:

Thank you very much for the so interesting table!  It is also very interesting for me what is the difference between the first two items?  What do these PROM/EPROM mean?

PROM is Programmable Read-Only Memory and EPROM, Erasable Programmable Read-Only Memory.  The critical difference in the comparison is the access times, not that one is a PROM and the other an EPROM. The 120-ns PROM of the first line is 3.75 times faster than the 450-ns EPROM of the second line. Perhaps the OS and/or benchmark programs are in PROM/EPROM. Others will know those details better than I.

...lee

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(And further to Lee's explanation) the access time is significant for your (Vol's) previous argument that the 9995 is only faster if executing from internal memory. I couldn't find a copy of the Intel application note referenced but we could be fairly certain that the instructions are being executed from EPROM (otherwise why mention them?). We don't know though whether the data is processed in internal or external RAM on the 9995 - although it must of course be external RAM with the 9900.

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And note that all processors are tested with 450nS EPROMs to eliminate one possible variable (speed of external memory).

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Posted (edited)

The reason for that they tested with 450 ns memory is that the TMS 9900 can't benefit from faster memory than that. That's a result of the two cycle memory access. For the TMS 9995, there are test results with the same kind of memory, but also with faster memory, which is required for the TMS 9995 to reach its max speed. The TMS 9900 runs at full speed with a 450 ns memory, but the TMS 9995 requires one wait state for each memory cycle under the same condition.

Thus you have to compare the TMS 9995 with 120 ns memory to the TMS 9900 with 450 ns memory to fully understand the speed gap between the two.

The distinction between EPROM and PROM is because when that table was written, TI didn't have any 120 ns EPROM technology. It took PROM to get there.

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It is quite easy to prove that the TMS9995 uses 12 MHz internally.  Just let's analyse its timings.  Its memory access cycle is 1 clock - this matches the 6502, ARM and 80486.  The TMS9995 is a CISC processor and a CISC processor can't have such timings in 1980.  So it is quite definite that actually the TMS9995 uses 4 clocks for a memory access - the same amount as the 8086, and 68000.  Indeed it is not the absolute proof but it is quite firm.
Maybe it is more correct to regard that the [email protected] is actually working at 12 MHz too? This is also Stuart's point.

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11 hours ago, vol said:

Maybe it is more correct to regard that the [email protected] is actually working at 12 MHz too? This is also Stuart's point.

Given it requires four different 3-MHz clock inputs, there's an argument to be made there.

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Posted (edited)

It depends on how you want to define it. Usually, one phase of a four-phase clock is used to trig a certain part of the design, so that four different sections in the CPU do their part of the work in the correct order, within one main clock cycle.

But if you look at each phase by itself, the frequency is still only 3 MHz, albeit with a duty cycle that's not 50%.

What's definitely true is that the 9995 will accomplish more in the same time than a 9900 can do.

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The only thing that really matters is the machine cycle time. All those numbers are presented in the specs. Don't get distracted by clock feeds.

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It depends on how you want to define it. Usually, one phase of a four-phase clock is used to trig a certain part of the design, so that four different sections in the CPU do their part of the work in the correct order, within one main clock cycle.

But if you look at each phase by itself, the frequency is still only 3 MHz, albeit with a duty cycle that's not 50%.

What's definitely true is that the 9995 will accomplish more in the same time than a 9900 can do.

Yeah, I do acknowledge that adding the clocks up would be a, umm, questionable thing to do. But you COULD do it!

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