Backplane Atari Computer

[ivop]

Hi,

 

Several times I have coined the idea of an Atari Backplane computer, so let's discuss this a bit. I would like to avoid bikeshed discussions and feature creep. The first thing to do, is to design the backplane and determine which signals should be available on the bus.

 

My idea is to put every Atari VLSI chip on its own card. That means, for example, that the AN Bus should be there for communication between ANTIC and GTIA. There could be a separate card for CPU, ANTIC, GTIA, ROM, RAM, MMU, POKEY, PIA, MIDI, SDrive, etc. Swapping cards should be a breeze. A backplane computer is basically a 1090, but with the computer on the same board. Hmm, like a 400/800

 

Here's my proposal for the backplane bus. What do you think? Any signals missing?

 

Discussion about connector type, or grouping of signals, etc... is an issue for later. First determine the bus signals. I'm at 78 signals now

 

 

 

Backplane Computer Bus.pdf

[ClausB]

I don't see any PORTA signals. Would the joysticks plug into the PIA board directly, or into the motherboard?

 

Also GTIA switch inputs, trigger inputs, keyboard circuit, etc.

Edited March 10, 2021 by ClausB

[ivop]

The idea is that the PIA board indeed has a pin header to bring out the signals to the connectors at the outside of the casing. Similar with the keyboard signals. Could be TransKey, could be lotharek's new USB AKI device. And the GTIA signals on a pin header.

 

I tried to keep signals that are only relevant to one particular task/card out of the bus. No joystick ports, no keyboard matrix, no GTIA csync/color/lum.

 

There's all the audio signals though. GTIA buzzer, SIO Audio IN, and Pokey L/R. One could opt for a dedicated audio mixer card, or let the Pokey card do the mixing.

 

Edit: or a case could be designed where the joystick connectors etc.. are soldered on the PIA card directly, and are connected to the outside world. But that's a discussion for later.

 

Question: which of these signals would benefit from being on the backplane bus and could be used by different cards? Convince me, and I'll add it

 

I added /REF and SYNC myself because I can imagine that, for example, a DMA card could need them.

Edited March 10, 2021 by ivop

[+DrVenkman]

I don’t want to add complexity to your concept, but how will you deal with bus capacitance from all these cards and the inherent signal propagation delays? ANTIC and GTIA, for instance, are usually very close together because FPhi0 is generated directly by GTIA and needs to be tightly coupled to ANTIC to be used to generate Phi0. That signal in term has to go to SALLY to create Phi2. Moving all these chips apart and hoping to keep things stable seems like it will have a number of challenges. 

[ivop]

To be honest, I have no idea how bus capacitance will affect this design. There are backplane computers that run at 8MHz, with clocks on the backplane bus.

 

I was hoping that a 4-layer 2mm backplane with power supply and ground/power planes, would be stable enough for up to 20cm long signals. Each card with ground fills, and they won't be big like EISA cards

 

 

Edited March 10, 2021 by ivop
typo

[danwinslow]

This sounds cool to me. Would there be general purpose slots...so for instance, for expansion? Or do I not understand...this is likely.

[ivop]

12 hours ago, danwinslow said:

This sounds cool to me. Would there be general purpose slots...so for instance, for expansion? Or do I not understand...this is likely.

Every slot is general purpose slot

 

I might decide though to put the AN Bus and the Fast clock at the end of the slot and route them to only three or four slots for CPU, ANTIC and GTIA.

[ivop]

Oh, found a missing signal! SIO COMMAND. Pretty important

[ivop]

79 signals, and a proposal how to layout the signals on several edge connectors.

 

AN/Unbuffered clocks -- 2x20 free -- Cartridge port -- SIO Bus

 

Now the question is, how to layout the remaining 39 34 signals on 2x20? Any ideas?

 

I hope it is clear that I'd like to separate the fast bus, because of earlier raised concerns. SIO has its own connector, so SIO only cards could be made. Cartridge bus has its own part of the slot. And 2x20 left for the rest

 

The CPU card, for example, does not need to connect to the SIO connector. But a SIO2SD card would only need the SIO part of the backplane bus. And an R-TIME8 cart could live on just the cartridge part. How to exactly layout the PCB that makes this possible, even with legacy carts, is a discussion for later

 

Edit: Wrong file. Attached the right one now.

 

Backplane Computer Bus v3.pdf

Edited March 11, 2021 by ivop

[Mathy]

Hello guys

 

On 3/10/2021 at 8:29 PM, DrVenkman said:

ANTIC and GTIA, for instance, are usually very close together because FPhi0 is generated directly by GTIA and needs to be tightly coupled to ANTIC to be used to generate Phi0. That signal in term has to go to SALLY to create Phi2.

 

Do we really need the clock signals all of these chips generate to come from these chips?  Or can we create some of these clock signals on the backplane?

 

Sincerely

 

Mathy

 

 

[+DrVenkman]

36 minutes ago, Mathy said:

Do we really need the clock signals all of these chips generate to come from these chips?  Or can we create some of these clock signals on the backplane?

I mean, I don't know. In terms of the system clock, it all starts with the crystal oscillator. The Atari architecture is fundamentally based around GTIA+ANTIC+SALLY all working literal lock-step with one another, tied together at the start by the OSC signal going into GTIA, which in turn provides Fast Phi0 to ANTIC, which then created Phi0 to send to SALLY. SALLY then provides Phi1 (used in the color generation circuit, if I recall correctly) and Phi2 used for almost literally everything else. If you want to divorce the chips from one another, by all means generate those signals wherever you like, but it's probable that strange results may occur if these chips don't all stay synchronized properly however you generate them. That said, why would you want to generate them separately? It's built into the silicon for each of these chips to generate the signals that they do with the inputs the receive from one another. But the fact that GTIA and ANTIC are the only ones that use FPhi0 are why they are physically side by side in every Atari computer ever built, and why SALLY and ANTIC/GTIA are on one card in the 800, but POKEY and PIA are on the motherboard.

[ivop]

OSC --> GTIA --> FPH0 --> ANTIC  --> PH0 --> SALLY --> PH1 and PH2

 

A buffered PH2 is fed back to both GTIA and ANTIC.

And indeed, PH1 is used for the charge pump that feeds the color adjustment pot back to the GTIA.

 

Trying to have that kind of synchronization with externally generated clocks is out of the question

 

Here's my latest PDF

 

I grouped signals by known "groupings". Hope I orientated the ECI right in regard to the cartridge port.

See page 3. Added some colors, too

 

 

Edit: each of those cards could be replaced by something else, as long as they continue providing the clocks back and forth. A new CPU card, new graphics cards, ...

 

Backplane Computer Bus v4.pdf

Edited March 12, 2021 by ivop

[ivop]

Another day, another PDF.

 

I decided to add two more spare signals to the I/O and MMU signals connector. One spare seems not enough. You never know what the future might bring.

 

Some other design decisions I made:

 

All connectors should be different. Not a chance you can plug in something wrong. Except for a cartridge the wrong way around Big fat front/back markings on the silkscreen.

 

Replicated CART/ECI and the PCB footprint should be compatible. You can plug in a CART/ECI card (SysCheck FTW!), or a single cartridge. Even C= shells (SIDE, etc...) should fit.

 

As per DrVenkman's concerns, the unbuffered clocks and the fast bus are on a separate connector that does not need to be routed to more than 3 slots, although another one or two slots would be nice. But not the full backplane.

 

 

I added a size column in mil. The whole bus, with proper gaps to fit CART/ECI etc..., is now 17.018 cm. I imagine the backplane to be 20cm x N, where N is >= 20 cm

 

Backplane Computer Bus v5.pdf

Edited March 12, 2021 by ivop
typo and clarification

[ivop]

Lovebyte weekend is over. Here's v6. Added two more spares to the fast/unbuffered bus, which is now 2x4 instead of 2x3. Also helped in sourcing parts   2x3 is hard to come by. Today I ordered ten pieces of each (2x4, 2x13, CART/ECI[2x15, 2x7] , 2x6). Price was less than €0.50 a piece for 50 card edge connectors. When I recieve them, I can check the spacing on a perfboard. Goal is a 20x20cm board with a power circuit and 10 slots 650 mil wide (for socketed chips overhang), and slots that's less than 17.5cm long.

Backplane Computer Bus v6.pdf

Edited March 15, 2021 by ivop

[ivop]

I received the edge connectors!

 

 

Now it's time to layout the backplane PCB

[danwinslow]

Nice!

[+ZuluGula]

@ivopwhere you ordered them?

[ivop]

I ordered them here:

 

https://www.aliexpress.com/item/4000490392119.html

 

They where packaged very well. No bent pins.

[+ZuluGula]

Thanks, I will be building couple of Atai ITX and 800XL computers and I will need them.

[ivop]

I just noticed they are even goldplated, although not shiny bright

 

Today I updated the bus specification. I added +12V to the PIA/MMU/Misc bus, so the GTIA card would not have to source +12V from the SIO bus. +12V instead of a ~10V charge pump used for the color signal.

 

I also laid out the bus on perfboards and adjusted the spacing/gaps between busses. Overhang is 150mil instead of 100mil. Adjusted for that. And increased the space between PIA/MMU/Misc bus and the CART bus. Even the widest carts should fit now.

 

Now some design considerations. I was thinking about leaving even the power supply of the main PCB. Just a bus on top, some GND or Vcc fills, and a full GND plane. The power supply will be just another plug-in card. Would that be dumb?

 

Also, I'm not sure yet if PIA and the MMU should live on one card, or on separate cards.

Backplane Computer Bus v7.pdf

[ivop]

Progress. I started laying out the PCB. Decided 9 slots instead of 10 was better. There needs to be enough room for the overhang of socketed chips. Overhang will be on the side that is marked FRONT on the CART slots, for example if you plug in a SysCheck in the CART/ECI to supply RAM and ROM.

 

 

This is just a prototype. It's 4 layers (ground and +5V power plane), and will be pretty sturdy if the PCB is 2mm thick. But later on I might have to sacrifice two SIO slots and one of the ANFU slots to make room for holes to screw this to a backplate/housing. And one or two screws somewhere in the middle of the board, to make inserting and especially removing cards less stressful to the PCB.

 

I renamed this to Project Jenny, to my late mother who died way too young , and in the tradition of Atari to name projects after women

 

Edited April 3, 2021 by ivop

[ivop]

Decided to add mounting holes. This is gonna be (to me) an expensive 4 layer board, so it should be right at the first time

 

 

Sacrificed two SIO slots, and moved the AN/Fast/Unbuffered bus a slot to the right. Still five slots. Only three will be used by the CPU, ANTIC and GTIA cards.

 

With a proper buffered cable, this board can also be used as a CART/ECI hub or a SIO hub. That's all nice, but I also did something extremely stupid. I overwrote my only copy of the bus proposal .ods file with an empty sheet Now I only have the v9 pdf. Now I have to type it over again. Sigh but LOL at the same time. How can you be so dumb after all these years

 

 

[+x=usr(1536)]

Hm.  It just occurred to me (and this is not a suggestion to necessarily do this; I'm only mentioning it before it exists my mind forever) that by consolidating components onto a smaller number of backplane cards, half of the physical space on that PCB could likely be used for laying out a 1090-compatible interface.  Might only get 3 or 4 1090 slots instead of the 5 that device was slated to have, but it would make for an interesting machine.  Sort of an Atari //XL

[Quiver]

7 hours ago, x=usr(1536) said:

Hm.  It just occurred to me (and this is not a suggestion to necessarily do this; I'm only mentioning it before it exists my mind forever) that by consolidating components onto a smaller number of backplane cards, half of the physical space on that PCB could likely be used for laying out a 1090-compatible interface.  Might only get 3 or 4 1090 slots instead of the 5 that device was slated to have, but it would make for an interesting machine.  Sort of an Atari //XL

Well why not make an atx form factor Atari? Combine both the 1090 and say the 1080 XEL. Though using the 576NUC as a base design has some attraction. Just some thoughts.

[+x=usr(1536)]

45 minutes ago, Quiver said:

Well why not make an atx form factor Atari? Combine both the 1090 and say the 1080 XEL. Though using the 576NUC as a base design has some attraction. Just some thoughts.

The idea's fine, but in keeping with the backplane concept, having integrated 1090-compatible slots makes for a best-of-both-worlds approach since it would allow for 1090 cards to be used either internally on this machine or externally on others with a PBI or ECI.  The form factor to do that internally doesn't exist in a 1088 or 576NUC, so anything around those dimensions would either need to grow to accommodate the cards or have them externally-connected via a 1090.

 

Of course, all of this is contingent on the 1090 seeing the light of day as a project.  There's been some recent motion on that, but there's still a great deal to be done, including development of the add-on cards.

 

Late edit: I just realised that you wrote ATX, not ITX.  Derp.  Yep, that could potentially be workable.

Edited April 6, 2021 by x=usr(1536)
Vowels are difficult