1090XL remake

[+kheller2]

8 boards?  The 1090 is only 5 slots in its last form.  RAM Banking on the 1090 is handled through a window, if you want to follow Atari's specs.

[reifsnyderb]

2 minutes ago, kheller2 said:

8 boards?  The 1090 is only 5 slots in its last form.  RAM Banking on the 1090 is handled through a window, if you want to follow Atari's specs.

Sorry, you are right.  5 slots.  I was thinking 8 because there are 8 possible id's.

 

RAM banking should still be through 4000-7FFF as far as I know.

 

[_The Doctor__]

That does not mean you couldn't have a legacy MIO and a 1090 also attached at the same time etc... and we can't assume a 5 slot 1090 was all that would have been... especially with a smart 1090 and sweet 16... Consider also the Idea that a CP/M card could also be made to stand alone with video card and the pbi could be it's expansion port so to speak as well.  We only see a couple of things that were heading towards production... we aren't seeing all of the prototypes and variants that existed. Curt was digging away at this at the same time he was trying to reclaim/find out where the calibration packs for the ginormous drives were so access to more of the data from Atari could be had... too many things being done at once and still have a family life... an amazing guy

Edited December 29, 2021 by _The Doctor__

[reifsnyderb]

4 minutes ago, _The Doctor__ said:

That does not mean you couldn't have a legacy MIO and a 1090 also attached at the same time etc... and we can't assume a 5 slot 1090 was all that would have been... especially with a smart 1090 and sweet 16... Consider also the Idea that a CP/M card could also be made to stand alone with video card and the pbi could be it's expansion port so to speak as well.

I am looking at using a CPLD so that the logic could be changed if necessary.

[reifsnyderb]

Something like this would work.  It's a work in progress so there needs to be some more capacitors added and the connections haven't yet been ran.  I've got to check some other connections, too, to see what else needs to be connected to the CPLD.  The big chip is a CPLD to take care of addressing, banking, and act as an EMMU.  The 4 other chips are 1MB SRAM chips.

 

I'd like to find some cheaper, more compact, memory but the next step is to use BGA packages where the clearances for running the connections are really, really tight and the via size is tiny.

 

The memory for this concept would cost about $35.  With BGA, the memory would cost less than $8.  

 

 

 

[kenames99]

6 hours ago, reifsnyderb said:

It is, yes.  It's on the 22nd page. 

 

There is a conflict on D1FE with something called the S-16 on page 26 and I am not sure what to make of it because the description on page 26 doesn't seem to match what the 1090 schematic is nor match the pinout of the parallel bus.  So I think it's safe to use the 22nd page and assume the S-16 description is unrelated.

ok, good. then if I quote from it you can always look it up. I did read in a document somewhere that indicated D!FE was for the IRQ but what you posted there says that it is D1FF on read. so I go with the Atari docs. also, some of the expansion cards do have a select swith on board to set their ID. the 80 column card does, so does the serial/parallel card, just to name a couple.

 

Ken

 

[kenames99]

2 hours ago, reifsnyderb said:

I am looking at using a CPLD so that the logic could be changed if necessary.

in this day and age I think that is the best way to go. I did the ram board as original as proof the 1090 was a viable option. it all works here and gives my 600XL computers 64k of ram.

 

Ken

 

[kenames99]

2 hours ago, reifsnyderb said:

Something like this would work.  It's a work in progress so there needs to be some more capacitors added and the connections haven't yet been ran.  I've got to check some other connections, too, to see what else needs to be connected to the CPLD.  The big chip is a CPLD to take care of addressing, banking, and act as an EMMU.  The 4 other chips are 1MB SRAM chips.

 

I'd like to find some cheaper, more compact, memory but the next step is to use BGA packages where the clearances for running the connections are really, really tight and the via size is tiny.

 

The memory for this concept would cost about $35.  With BGA, the memory would cost less than $8.  

 

 

 

just out of curiosity, what cpld are you using?

 

Ken

 

[reifsnyderb]

13 minutes ago, kenames99 said:

just out of curiosity, what cpld are you using?

 

Ken

 

ATF1504 -- The 100 pin variety.

[reifsnyderb]

14 minutes ago, kenames99 said:

just out of curiosity, what cpld are you using?

 

Ken

 

ATF1504AS-7AX100

[reifsnyderb]

Here's a possible 2MB SRAM module for the 1090.  This module uses 3.3 VDC and has level shifting chips.  (I decided to do one with 3.3 VDC as a lot of chips are now 3.3 VDC.)  This SRAM chip IS61WV102416FBLL-10T2LI is actually 1MB x 16.  Since the high 8 bits and low 8 bits can be selected separately it can supply the Atari with 2MB of RAM.

 

I'll finish up the 4MB SRAM module as well.  That uses 5 VDC chips but would be more expensive to make.

 

If there is enough interest I'll make up some boards for proper CPLD programming and testing.

 

 

  

[rkindig]

Interested in the 1090 and any boards for it!

 

Randy

host Floppy Days Podcast Floppydays.com

[reifsnyderb]

...and here is a possible 4MB memory board.  The CPLD logic needs created, of course.  The simple solution to the memory banking is to use Axlon style memory banking but at D1FE.  The window would be at the usual 4000-7FFF.

This is with 5 VDC components.  The memory chips are AS6C8008.

 

 

 

 

 

[atari-passion]

 

Would the card be directly compatible with all programs using more than 64kb of memory ?

 

 

Edited January 2, 2022 by atari-passion

[reifsnyderb]

11 minutes ago, atari-passion said:

 

Would the card be directly compatible with all programs using more than 64kb of memory ?

 

 

I've been thinking about this.  If D1FE only is used for banking then the answer is no.

 

However, after some thought, I think there could be mirror registers programmed into the CPLD as parallel cards can operate completely independently of the MMU.  So, if the memory card is also monitoring CFFF and PORTB while ignoring PB_EXTEN_B only for these two addresses I think this could be arranged.  CFFF is the last address of the XL's international character set.  However, the MMU maps it to the ROM.  So, if you were to write to CFFF I think it would be ok.  It wouldn't change the ROM.  So if the CPLD were to allow writes only to CFFF then banking could be set and a read of CFFF would be the last byte of the international character set.  I think this would work. 

 

The same would go for PORTB.  I think that if the parallel card were to monitor PORTB and set the bank depending upon what is written to PORTB compatible banking could happen.  However, PORTB wouldn't allow for the entire 4MB banking as writes to PORTB would also result in the MMU responding to these changes.

 

[+DjayBee]

Do you have enough gates on the CPLD and the needed signal lines to decode the following? 

 

Add two jumpers to select 

- 4 MB D1FE banked

- 3 MB D1FE plus 1 MB Axlon

- 3 MB D1FE plus 1 MB Rambo/U1MB

- 3 MB D1FE plus 1 MB CompyShop

 

Regarding CFFF in Axlon mode:

- If access comes from ANTIC then I suppose HALT is active. Ignore the request so ROM data is returned. 

- Same if access comes from E000-EFFF. This should be safe because Axlon is an extension for the 800 which cannot switch off the ROM. 

- Otherwise return the CFFF register's value. 

[reifsnyderb]

12 minutes ago, DjayBee said:

Do you have enough gates on the CPLD and the needed signal lines to decode the following? 

 

Add two jumpers to select 

- 4 MB D1FE banked

- 3 MB D1FE plus 1 MB Axlon

- 3 MB D1FE plus 1 MB Rambo/U1MB

- 3 MB D1FE plus 1 MB CompyShop

 

Regarding CFFF in Axlon mode:

- If access comes from ANTIC then I suppose HALT is active. Ignore the request so ROM data is returned. 

- Same if access comes from E000-EFFF. This should be safe because Axlon is an extension for the 800 which cannot switch off the ROM. 

- Otherwise return the CFFF register's value. 

I have enough signal lines and could add jumpers.  I can't answer the question regarding gates as I don't have a way to see how many are left.  I can only say for certain the CPLD I am using has 64 macro cells.  Also, with the 800XLM (and 600XLM boards), the MMU CPLD was fine with all the gates I had to add and it only had 32 macro cells.  In some respects this memory board CPLD is easier than the MMU.  However, there will need to be 8 JK-flip flops (8 macro cells??) used so as to save the banking register and there will need to be decode logic so as to allow a access to the banking register if the correct address is selected.

 

Jumpers may not be needed.  Consider this possibility:

  1.  D1FE allows for the selection of any bank.  (256 banks possible or 4 MB)  The problem here is that nothing was written, that we know of, that banks memory via D1FE.  We only have the specification.

  2.  CFFF (Axlon) allows for the selection of any bank.  (256 banks possible or 4 MB)  There is the conflict with the international character set part of the ROM. 

        (There are other hardware registers that are used to store a value for one thing and read a value for something entirely different.  I don't think this would be a problem to do this here too.)

  PORTB allows for the selection of 16 banks if bits 2,3,5,6 are used.  (16 banks or 256k)  Other bits couldn't be used because there is no way to control the MMU and it's chip selects.

 

The easiest way for a parallel port memory card to work would be for it to completely replace the internal memory.  Arguably, 64k is wasted if an 800XL is connected to the 1090 with such a card.  This is where adding a jumper could come in handy so as to let the parallel port know if you are connecting to a 16k 600xl or a 64k 800xl if there is a concern about still using the internal memory.  My feeling is that it's more plug-and-play to not worry about the Atari's internal memory and just replace it with the card.

 

I am thinking the biggest reason an Axlon style memory banking scheme couldn't be used on an XL is because the MMU would always direct writes to the ROM and it would, of course, fail.  I could be wrong and if somebody who knows more could chime in here that would be great.

 

I don't see a way to tell if access is coming from ANTIC or the CPU.  HALT doesn't extend through the parallel bus, unfortunately.  I don't believe that banking ANTIC is possible.  However, it's my understand that banking ANTIC is more of an edge case as it wasn't used much.

 

It would be easy enough to have the memory card CPLD only handle write requests to CFFF.  However, a read to CFFF would return the ROM value if the CPLD would ignore it.  (If the CPLD would try to return the value there would be a conflict, of course.)

 

 

[Mathy]

Hello guys

 

How is the extra memory in the MIO accessed?  IIRC, the MIO can access 16MB with the new firmware.  Using the MIO methode might circumvent most of the problems we have with all the other methodes (when used in 1090 memory cards) and enable us to keep using the internal extended RAM in the computer.  And you could have 16MB and the ability to read from the memory expansion which bank/part of memory is being accessed.

 

Sincerely

 

Mathy

 

[+David_P]

MIO RAM is accessed 256 bytes at a time through $D6XX, set through $D1E0 (A15-A8) and $D1E2 (A19-A16).  See http://websites.umich.edu/~archive/atari/8bit/Info/Hardware/mioman.txt chapter 5.

[reifsnyderb]

Are there a lot of MIO devices around?  After a quick scan of the MIO system it appears they didn't follow Atari's standards.

[+David_P]

There are the original MIOs sold by ICD and those produced by @MetalGuy.  At the time of the MIO release, the only other PBI devices out were RAM expansions for the 600XL.  Even now, there are not many other PBI devices available: there's the Black Box; Supra HD; BTL HD; various versions of the IDE Plus; the Yorkie 256K expansion; a 320K RAM expansion...

 

As they were all pretty much designed as stand-alone devices, in the absence of the 1090 or any other official Atari devices, each pretty much took control of the bus for its own purposes, regardless of the Atari standards.

[reifsnyderb]

I might stand corrected.  MIO may be compatible with the 1090.  (I looked at the wrong addresses.)  D1E0 through D1E7 was reserved by Atari and, therefore, probably ok for the MIO to use.  A closer look would be required.

 

[kenames99]

the MIO kinda did and kinda didn not. it did not use /EXTENB signal at all whick is a core part of the Expansion bus protocol. the rest was done pretty ok considering each card has full access to D1xx page since only it's own hardware is enabled and all other "slots" are not enabled so those are inaccessible. also, the mio used 2 of the other D1FF bits to access it's menu to download into system ram, so there is that. that takes away 2 other banks.

 

Ken

 

[Mathy]

Hello Ken

 

The MIO had a menu, but the MIO was more than a memory extension.  If you create a new memory extension, you don't really need a menu.  We only need the memory extension part.

 

Sincerely

 

Mathy

 

[reifsnyderb]

2 minutes ago, Mathy said:

Hello Ken

 

The MIO had a menu, but the MIO was more than a memory extension.  If you create a new memory extension, you don't really need a menu.  We only need the memory extension part.

 

Sincerely

 

Mathy

 

If the MIO didn't do anything with CFFF, 1DFE, or PORTB then my proposal will be compatible.