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jedimatt42

Do we have the Rave99 speech adapter PAL equations?

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I've got a board without the PAL.. would like to make it functional again... before I reverse engineer this, do we already have the equations that could be translated to a GAL?

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Posted (edited)

I've mapped out the following pinout for the PAL

 

         +------+
DBIN -> (1)   (24) -- VCC
AMC  -> (2)   (23) <- MEMEN*
AMA  -> (3)   (22) -> LED*
AMB  -> (4)   (21) -> SBE
A1   -> (5)   (20) -> 74'245-DIR
A0   -> (6)   (19) -> SPCH_A5
A3   -> (7)   (18) -> SPCH_A15
A2   -> (8)   (17) -> 74'245-OE
A5   -> (9)   (16) -> RBDENA
A4   -> (10)  (15) -> READY
A15  -> (11)  (14) <- SPCH_READY (EDIT)
GND  -- (12)  (13) -- NC
         +------+

 

Edited by jedimatt42
Pin 14 is input from speech synth READY signal

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Posted (edited)

My first guess: 

 

SBE <= !MEMEN && A0..A4 == 0b10010 && !A15 && AMA..AMC == 0b111 && !(A5 && DBIN)

LED <= !SBE

SPCH_A5 <= A5

SPCH_A15 <= A15

74'245-OE <= !SBE

74'245-DIR <= DBIN

RBDENA <= !SBE

RBDENA.OE <= !SBE

READY <= This one surprises me, so probably wrong..  ( I'll pretend this is for purposes of buffering output from synth's READY )

 

It is not apparent to me why A5 is buffered through the PAL, unless it is also worked into something else... combined with DBIN for agreement? 

Edited by jedimatt42
Wisdom from FarmerPotato, also I forgot MEMEN, and RBDENA-tristate, and NAND is not the same as not-equals, and it doesn't work still.

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Posted (edited)
5 hours ago, jedimatt42 said:

 

It is not apparent to me why A5 is buffered through the PAL, unless it is also worked into something else... combined with DBIN for agreement? 

Think of read before write. SBE must not activate during a read from the write address. A5 distinguishes 9000 from 9400. Its why we have separate blocks for read and write. 
 

I wondered why WE is not in there. Guess it goes straight to the 5200?

Edited by FarmerPotato
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I can hard code the LED on ( 'b'0 ) so that works..

I think the '245 dir might be inverse of DBIN. But I'm tired, so I'll try that tomorrow.

 

If I force READY to 'b'0, I get the nice F18A init screen since no CPU written to it yet. But I have bus clash right now... 

 

Besided having forgotten A5 vs DBIN, I had forgotten the MEMEN* signal too :)  LOL...

 

getting closer.

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