Hard Disk DMA Question

[TGB1718]

I'm having some issues with a SD interface for my ST's (STM and STE), neither seem to work with it.

So I was thinking it may be the 3.3V of the controller (STM32) which is not good enough to

properly drive the ST's.

 

I want to build an interface that has bi-directional level shifters but also needs to isolate the

bus when not in use (using 74HCT245 Octal bi-directional tri-state buffers).

 

Does anyone have a good timing diagram of all the signals during read/write operations to

the hard disk as I need to turn the output off when DMA is not for the hard disk.

I've read loads of articles, but nothing is quite clear enough. I wanted to know if the CS signal

 becomes active for the duration of all hard disk operations, if so then this is the signal I need

to use, but I can't seem to find anything that confirms this.

 

It may be this with a combination of some of the other signals.

 

Any help will be much appreciated.

[ParanoidLittleMan]

In last weeks I did read lot of bad things about this new ACSI adapters for SD cards, unreliable work, then some work good only with ST, some with STE, etc. From users self, not some 'experts' .

There are some timing diagrams in Atari ST Profibuch, 1987 edition (not present in later ones). I used them for driver SW write, for designing ACSI-CF adapter. But there are at least 2 smaller mistakes on those timing diagrams. And I don't know about some better ones.

I can put them om my site, with some comments, translation to English by need.

And must say that doubt that level shifters, line drivers will make it much better.  Lot of people just ordered UltraSatan after all hassle. Or some other proven device.

"I've read loads of articles, but nothing is quite clear enough." - Agree 100% . Only thing what is clear for me today is that this disease and all around it had serious impact on human brains, social behavior, and seriously, how low can we sink ? It is like common sense (or in my native languages (there is 2) healthy peasant sense) getting to disappear. So much lies, so much hypocrisy. Already worse than what was presented in Idiocracy.

 

[TGB1718]

16 minutes ago, ParanoidLittleMan said:

I can put them om my site, with some comments, translation to English by need.

Yes please and thank you

[ijor]

The official Atari timing and specification were published in a couple of documents available at https://docs.dev-docs.org/

 

I think the main ones you might be interested to check are:

 

- Engineering Hardware Specification of the Atari ST Computer System

- Application Notes on the Atari Computer System Interface (ACSI)

- Atari ACSI/DMA Integration Guide

 

Official specs are not always the best and sometimes are even not 100% correct, but they are important to check nevertheless.

 

21 hours ago, TGB1718 said:

I want to build an interface that has bi-directional level shifters but also needs to isolate the

bus when not in use

You must disconnect from the bus when not needed. Among other reasons because on some ST models the bus is internally shared with the floppy interface.

 

[TGB1718]

1 hour ago, ijor said:

- Engineering Hardware Specification of the Atari ST Computer System

- Application Notes on the Atari Computer System Interface (ACSI)

- Atari ACSI/DMA Integration Guide

Many thanks @ijor, the last 2 documents have all the information I require

 

[ParanoidLittleMan]

OK, so no need that I make photos from book, which is not in some good shape btw.  And there are more details on that diagram in ACSI_DMA guide, although my neck did not like orientation ?

However, I don't see timing diagram of DMA transfer self (so transferring 512 bytes) without SW intervention - anywhere.

In any case, CS signal is not used in DMA transfer phase, for sure.

Considering bus isolation - it is isolated by using 3-state chips. I mean word isolation is not really good. In my opinion main problem is interfacing old, slow TTL logic with modern, way faster and CMOS logic chips.  Bus is partially shared with floppy, but DMA chip is what is shared too.  Funny thing is that there were no problems with ST machines where no line buffers to DMA connector, and were in case of STE where are line buffers.