laoo Posted June 13, 2021 Share Posted June 13, 2021 (edited) Hi! Sorry for dumb question, but I'm very ignorant with respect to electronics etc and for my "secret project" I need to know how conflicts on the wire are detected. Does the hardware detects on electric level that both sides are transmitting? Or only when one side transmits 1 and the other side 0? Or maybe only when received packet isn't correct (wrt start bit and stop bit)? I know that I should study all this UART stuff on electric level first, but I'm afraid I'm too dumb for this and I sense that it's simple enough that few sentences from someone educated should help me. Thanks in advance. Edited June 13, 2021 by laoo Quote Link to comment Share on other sites More sharing options...
sage Posted June 13, 2021 Share Posted June 13, 2021 yes. that is the unreliable principle. better use checksumming in addition. Quote Link to comment Share on other sites More sharing options...
42bs Posted June 13, 2021 Share Posted June 13, 2021 There is no detection at all. All Lynxes are on the same line. So collision detection must be done in software. The hardware detects framing error IIRC. Quote Link to comment Share on other sites More sharing options...
laoo Posted June 13, 2021 Author Share Posted June 13, 2021 (edited) I presume that framing error is when the lynx does not read proper stop bit at 10th bit after start bit. What i'm also interested is what happens on the wire, when: 1. Two lynxes send 1 2. Two lynxes send 0 3. One lynx sends 0, the other 1? Edited June 13, 2021 by laoo Quote Link to comment Share on other sites More sharing options...
42bs Posted June 13, 2021 Share Posted June 13, 2021 The line is like an OR, so if any Lynx puts a 1 on the line the result is a received 1. This might cause an parity error. Since TX and RX are connected you see the echo of the sent data. So you can detect collisions also. But IMHO a checksum is the best method. It worked great in T-tris and I think Sage has also good experience with it. Quote Link to comment Share on other sites More sharing options...
laoo Posted June 13, 2021 Author Share Posted June 13, 2021 (edited) Thanks for your answers. I was missing one piece of whole picture: the idle state is logical 1. Hence the start bit being 0 triggers receiver to start shifting bits of the value and stop bit being 1 just resets the trasmission to idle state. Frame error is triggered when there is no stop bit (1) at 10th bit after start bit (0) and break is after many zeros. That all make sense now. Edited June 13, 2021 by laoo Quote Link to comment Share on other sites More sharing options...
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