E-Bus System Design Handbook (for Powertran Cortex)

[+Ksarul]

This is a generally unobtainium manual for the Cortex. The E-Bus is the Cortex's expansion bus, but it was rarely used due to the general impossibility of sourcing the 74LS2001 Bus Arbiter chip. A few smart folks used the system design handbook to design simple workarounds to allow limited use of the bus, and that allowed several expansions to see the light of day. The manual itself nearly disappeared though, as only a handful of physical copies are suspected to survive. I received this scan of one of those copies a few years ago, and realized today that it still doesn't seem to be readily available online. This should probably also be put in with the Cortex files on WHT.

E-Bus_System_Design.pdf

[+FarmerPotato]

This was very interesting, thank you.

 

I don't understand how the 9901 works with the interrupt multiplexing though.

[+FarmerPotato]

@Ksarul

i would like to know more about what difficulties that Cortex owners had with expanding to e-bus. 
 

At first look, it doesn’t seem to require anything special if you have only one bus master like a cpu. unless slave devices can contend for replying at the same address (!)

If you want DMA, say from a disk card to memory on the bus, then you have two bus masters and need the arbitration logic. 

 

However I still don’t get how interrupt codes are supposed to reach the cpu or 9901.
 

Something has to have 128 interrupt bits latched, (16 per card slot) and tell the cpu one of 16 levels thru a priority encoder feeding CC0-CC3 and INTREQ. Then the cpu has to figure out what card the interrupt is from, in order to service and clear it. 
 

the sender of the interrupt needs a lot of logic too. 
 

is this stuff all solved somewhere? I think maybe the 8086 works this way?

 

if I were adopting partly the e-bus, I would add plain old multiple bus lines one for each interrupt. Maybe one per card, settable per slot like on the 990.(e bus leaves 33 lines reserved for future.)

 

And also switch one of the unwanted voltage rails to 3.3V…

 

 

 

 

[+Ksarul]

The best set of answers to your questions are the ETI articles that laid out the Cortex design and some of the E-Bus expansions, @FarmerPotato. They're available online at http://www.powertrancortex.com/. Look at the two parallel interface articles to see what the E-Bus Arbiter workarounds worked like.

[+FarmerPotato]

Yep, there’s the goldmine. 
 

but they managed to make their own website less readable than the magazine scans. Yikes. (All Comic Sans — translates to fancy script on iOS.)
 

A PAL16R8 chip looks capable of replacing the 74LS2001.  Aside from the weird pin out, I see mention that the 2001 was just a programmable logic device??

 

 

Edited September 5, 2021 by FarmerPotato

[+Ksarul]

On 8/13/2021 at 9:07 AM, FarmerPotato said:

A PAL16R8 chip looks capable of replacing the 74LS2001.  Aside from the weird pin out, I see mention that the 2001 was just a programmable logic device??

I came to the same conclusion a while ago. The TI patent for the bus arbiter is online. The most important part of that is that it contains a logic diagram that shows how the E-Bus arbiter is internally arranged--gate by gate. Build the combinatorial logic to program the chip and match the signal names to the appropriate pins on the chip to replicate the 74LS2001 and you'd have a fully functional bus arbiter chip.

[+FarmerPotato]

21 hours ago, Ksarul said:

I came to the same conclusion a while ago. The TI patent for the bus arbiter is online. The most important part of that is that it contains a logic diagram that shows how the E-Bus arbiter is internally arranged--gate by gate. Build the combinatorial logic to program the chip and match the signal names to the appropriate pins on the chip to replicate the 74LS2001 and you'd have a fully functional bus arbiter chip.

 

Still looking for that patent. Any keywords to pinpoint it?

 

I searched for Texas Instruments, Bus Arbiter and some variations.

 

The closest I got was this 1985 patent which describes a token-ring bus arbiter. https://www.freepatentsonline.com/4730268.pdf  It's still pretty cool. (I see more bus arbiter patents from 2000 onward.)

 

In #4730268 Distributed Bus Arbitration For A Multiprocessor System, a ring of (perhaps 4) arbiter chips will move a 1-bit access token around the ring in less than one clock cycle. Arbitration is achieved within one cycle.

 

A CPU can use the bus if it has the token, but afterward hands it to the next in the ring. Because of this, nobody gets starved out.

 

Potentially, no bus cycles are wasted: Another CPU can fetch or store while one CPU is doing an internal ALU cycle.  I think no CPUs need be put into a HOLD state, only single wait states. A CPU's bus drivers can be tri-stated until the arbiter grants access.

 

Contrast this with E-Bus, where priority is strictly ranked: a higher priority card gets access before a lower priority card. The lower priority card must complete its current operation, and get off the bus.

 

[+Ksarul]

Here's a copy of it that I put up on WHT ages ago, as part of the 74LS2001 documentation.

74LS2001 E-Bus Arbiter US4633392.pdf

[+FarmerPotato]

There’s a lot of things that don’t make sense to me about E-Bus. 
 

I understand the arbitration sequence, but not how a 9900 could use it. CRU reads look like idle states, so nothing to trigger a bus request.  99105 has adequate information in the Bus Status codes. 
 

Timing is slow if BUSCLK is 3 MHz. The design guidelines indicate that higher speeds (limited to 10MHz) require a 4 layer backplane. 
 

It takes at least two rising  edges of BUSCLK before a bus access can begin. That’s two wait states added to every bus access (given 3MHz.) That’s before any waitstates for the memory. 

 

it’s a bigger disaster for the 99105 at 6MHz. To meet memory timing at 6MHz, the early read/write signal must get out to the bus, well, early. 
 

I imagined there would be a way for 2 equal CPUs to interleave access to the main bus, but I don’t see how that’s possible in an efficient way.  

 

More questions than answers. 

. 

 

 

[+FarmerPotato]

So I haven't given up on E-Bus yet.

 

I tried to find more information about TI E-Bus modules. I found this document which briefly mentions 990/E350:

https://www.aconit.org/histoire/iga_boucher/pdf/Vol_D_549-696.pdf

Starting on Page 35, in a long article concerning Texas Instruments:

 

Quote

Catalogue informatique – Volume D - Ingénieur Général de l'Armement Henri Boucher Page : 35/381

 

En 1980, la filiale allemande de Texas reprendra cette idée de modules en proposant des cartes analogues au format Eurocard de 100 * 160 mm, enfichable dans les chassis du bus multiprocesseur européen, conçu pour 1 MB d'adresses , des données de 8 ou 16 bits, et les interruptions dues à leurs périphériques. On y trouve une carte processeur ( E 150 ), une carte mémoire de masse ( E252, pour 92 Kbits de mémoire à bulles). deux cartes d'entrées / sorties ( E350, E351), et une carte fond de panier ( E501), ainsi que le même petit terminal et le même logiciel qu'aux USA. On peut penser que cette décision est l'indice d'un réel succès, confirmé par deux annonces commerciales trouvées dans Electronics, concernant des convertisseurs A / N de Analogic Corp. et Analog Devices, présentés pour s'intégrer à la famille.

 

Voir tous ces documents dans une chemise de la boite 113, avec leurs tarifs.

 

Google Translate with a bit of patch-up:

 

Quote

In 1980, the German subsidiary in Texas took up this idea of modules by
offering analog cards in Eurocard format of 100 * 160 mm, pluggable into the
European multiprocessor bus chassis, designed for 1 MB addresses, 8
or 16 data bits, and vectored interrupts from peripherals. 

 

There is a map processor (E150), a mass memory card (E252, for 92 Kbits
of bubble memory), two input / output cards (E350, E351), and a
backplane card (E501), as well as the same small terminal and the same
software as in the USA. We can think that this decision is the sign of a
real success, confirmed by two commercial announcements found in
Electronics, regarding A / D converters from Analogic Corp. and Analog
Devices, presented to fit in with the family.

 

See all these documents in a folder in box 113, with their prices.

 

 

From the E-Bus System Design Handbook (in this thread) chapters 6 and 7 give examples from cards:

 

E150 is a single processor module at 2.5 MHz with 6 interrupt levels. 

E155 Microcomputer module  3MHz

E5012 Backplane (typo?)

E350 IN module

E301 Microterminal

 

As to the book, there's a lot more, grossly inaccurate concerning things we know about, that I would not rely too much on the book's whole 30 pages about Texas Instruments. (pages 19-51)

 

Quote

After this purely technical-commercial interlude, TI resumes the IT offensive in 1979 by creating new products: the TI 99/4 home computer and the TI 990/12 business computer.

 

And here's where I think less of this report (me: translation cleaned up)

 

Quote

The 99/4 is a compact tabletop model, devoid of monitor, because it operates with a television. See sheet.

 

Despite using the TI 9900 processor, this technology is a little underused. This is why, in 1982, TI tries to develop it, under the name of BS 200,  into a business terminal  available in various versions depending on the choice of discs. Small success.

 

With profits falling, TI will offer in 1983 the TI 99/2, which is nothing more than a
99/4 at a bargain price, opportunity to sell some peripherals. But the PC is there,
now, and other home computer standards, even though cheaper, do not have its appeal. The 99/2 will hardly sell.

 

 

Edited November 24, 2021 by FarmerPotato
Continued into 99/4. Family Calculator = Home Computer

[+Ksarul]

There were several E-Bus cards made for the Cortex as well: I know of a memory card, a serial/parallel card, a serial card with additional joystick ports, and an MFM Hard Disk Controller card.

[+FarmerPotato]

Continuing to search "Electronics" magazine for E-systems, or any TM990 references, like this one. The French book named TM990/E252 as a 92KiBit bubble memory card.

 

 

Quote

 

[Electronics, Feb. 14, 1980, p. 40]

 

TI readies first standard product with megabit bubbles

The first standard product to use Texas Instruments Inc.'s megabit magnetic-bubble memory device is slated to roll out of the Dallas company this month. The TMS 990/211 module will employ up to six TIB 1000 bubble chips, providing 768 kilobytes of nonvolatile storage per card for use in TMS 990 microcomputer systems. The 211 board is the first in a series of 990-compatible modules planned to utilize the TI family of 256-K, 512-K, and 1-Mb bubble chips announced at Wescon last year [see Electronics, Sept. 27, 1979, p. 37].

 

 

128Kbytes/chip?  1Megabit. Yup, checks out. You can guess why TI execs thought bubble memory was going to be huge, if it offered 1 MBit density at a time when 4K and 16K was common. In 1980,  256K DRAM became the cutting edge. And then bubble memory collapsed. 

 

 

 

 

[JB]

Lotta people were caught up in the bubble memory bubble when it popped.

[+FarmerPotato]

This is likely an E-Bus compatible CPU module.

 

The picture shows a card with two DIN-41612 connector, which makes it a Double Eurocard. The double format shown on page 8-7 of the E-Bus systems manual is 233.4mm on the front panel side, extending 160mm to the backplane. This system appears more like 233.4mm high and 100mm deep, which is also a valid format.

 

The double connector goes to two separate busses, for instance having a second bus just for I/O expansion. The TI E-Bus uses 57 pins of the 64-pin DIN-41612 connectors.

 

 

[Electronics, Jun 5, 1980, p. 200]

 

TI 990 gets software-compatible board

 

The model CPU-200 microcomputer board from Erni & Co. is based on Texas
Instruments' 16-bit TMS9900 microprocessor. It provides the central
processing functions for Erni's recently announced 990E industrial
microcomputer system software while offering software compatibility
with TI's 990 minicomputers and microcomputers. The CPU-200 features a
56-line proprietary bus that allows memory addressing of up to 64
kilobytes and input/output capabilities by using the TMS 9900 bit-serial
communications register unit. Up to 4,096 inputs and outputs may be
addressed individually. An RS-232 or current-loop serial port is
provided.

 

The unit also features 16 vectored interrupts, an eight-line bit
programmable port, and an internal timer. It operates at 3MHz. The
external control functions of the TMS 9900 are available to the user.

 

The board sells for $560.

 

Erni & Co., 3316 Commercial Ave., North- brook, I. 60062. Phone (312) 480-9240 [341]
 

 

 

[Jimhearne]

Is this the Patent you were looking for ?

 

This is my replacement for the 74LS2001 in the Cortex , it's a surface mount version of the 74LS2001 replacement from the ETI article.

 

I seem to remember the Cortex just uses INTEN line on the Ebus as a single interrupt, it doesn't place a interrupt code on the bus which the full E-Bus implementation would.

On my TMS99105 E-Bus system i got as far as sending the Interrupt code on the bus and reading it into a register on the processor card but then the processor needs to read the interrupt code at a certain point in the interrupt code and i got a bit stuck at that point.

This was over a year ago so my memory is a bit hazy, i've moved house since and all the E-BUS stuff is still packed up waiting for my new workshop to be finished.

 

I've a small collection of other E-BUS cards:

TI TMS990E150 TMS9980 processor card 

A couple of TI  TMS990E251A Ram cards

A MPE CPU-E   TMS9995 processor card

A MPE DRAM-E Dynamic ram card

A MPE PIO-E parallel port / joystick card, the same as the one in ETI

A MPE FD/WD-E FDD and HDD controller, this talks to a WD-1002 series control card which in turn talks to a MFM hard drive and floppy drive.

 

I've a lot of scanned documentation for the MPE cards including some schematics.

 

Jim

 

74LS2001 E-Bus Arbiter US4633392.pdf

[Jimhearne]

Sorry, i see Ksarul already listed the patent, missed that message on my first reading of this thread.

 

Jim

 

[+Ksarul]

6 hours ago, Jimhearne said:

Sorry, i see Ksarul already listed the patent, missed that message on my first reading of this thread.

 

Jim

 

Yes, it is the same one. Three pages in the middle of the document make up a complete block diagram of the original 74LS2001 chip. I probably need to take that and make a schematic of it with the pins identified by number and name, as that may come in useful if anyone ever tries to replicate the entire chip. I like your solution replicating the ETI workaround too.

[+FarmerPotato]

On 4/6/2022 at 6:36 PM, Ksarul said:

Yes, it is the same one. Three pages in the middle of the document make up a complete block diagram of the original 74LS2001 chip. I probably need to take that and make a schematic of it with the pins identified by number and name, as that may come in useful if anyone ever tries to replicate the entire chip. I like your solution replicating the ETI workaround too.

I’ve moved on from studying the LS2001.  I compared the Intel Multibus arbiter chip from a few years earlier. Both have sub optimal behavior. 
 

Im interested in TI’s NuBus arbiter. It’s more capable of Fair scheduling.