Jump to content
Sign in to follow this  
Ksarul

E-Bus System Design Handbook (for Powertran Cortex)

Recommended Posts

This is a generally unobtainium manual for the Cortex. The E-Bus is the Cortex's expansion bus, but it was rarely used due to the general impossibility of sourcing the 74LS2001 Bus Arbiter chip. A few smart folks used the system design handbook to design simple workarounds to allow limited use of the bus, and that allowed several expansions to see the light of day. The manual itself nearly disappeared though, as only a handful of physical copies are suspected to survive. I received this scan of one of those copies a few years ago, and realized today that it still doesn't seem to be readily available online. This should probably also be put in with the Cortex files on WHT.

E-Bus_System_Design.pdf

  • Like 5
  • Thanks 1

Share this post


Link to post
Share on other sites

@Ksarul

i would like to know more about what difficulties that Cortex owners had with expanding to e-bus. 
 

At first look, it doesn’t seem to require anything special if you have only one bus master like a cpu. unless slave devices can contend for replying at the same address (!)


If you want DMA, say from a disk card to memory on the bus, then you have two bus masters and need the arbitration logic. 

 

However I still don’t get how interrupt codes are supposed to reach the cpu or 9901.
 

Something has to have 128 interrupt bits latched, (16 per card slot) and tell the cpu one of 16 levels thru a priority encoder feeding CC0-CC3 and INTREQ. Then the cpu has to figure out what card the interrupt is from, in order to service and clear it. 
 

the sender of the interrupt needs a lot of logic too. 
 

is this stuff all solved somewhere? I think maybe the 8086 works this way?

 

if I were adopting partly the e-bus, I would add plain old multiple bus lines one for each interrupt. Maybe one per card, settable per slot like on the 990.(e bus leaves 33 lines reserved for future.)

 

And also switch one of the unwanted voltage rails to 3.3V…

 

 


 

 

Share this post


Link to post
Share on other sites

The best set of answers to your questions are the ETI articles that laid out the Cortex design and some of the E-Bus expansions, @FarmerPotato. They're available online at http://www.powertrancortex.com/. Look at the two parallel interface articles to see what the E-Bus Arbiter workarounds worked like.

  • Like 2

Share this post


Link to post
Share on other sites
Posted (edited)

Yep, there’s the goldmine. 
 

but they managed to make their own website less readable than the magazine scans. Yikes. (All Comic Sans — translates to fancy script on iOS.)
 

A PAL16R8 chip looks capable of replacing the 74LS2001.  Aside from the weird pin out, I see mention that the 2001 was just a programmable logic device??

 

 

Edited by FarmerPotato
  • Like 2

Share this post


Link to post
Share on other sites
On 8/13/2021 at 9:07 AM, FarmerPotato said:

A PAL16R8 chip looks capable of replacing the 74LS2001.  Aside from the weird pin out, I see mention that the 2001 was just a programmable logic device??

I came to the same conclusion a while ago. The TI patent for the bus arbiter is online. The most important part of that is that it contains a logic diagram that shows how the E-Bus arbiter is internally arranged--gate by gate. Build the combinatorial logic to program the chip and match the signal names to the appropriate pins on the chip to replicate the 74LS2001 and you'd have a fully functional bus arbiter chip.

  • Like 2

Share this post


Link to post
Share on other sites
21 hours ago, Ksarul said:

I came to the same conclusion a while ago. The TI patent for the bus arbiter is online. The most important part of that is that it contains a logic diagram that shows how the E-Bus arbiter is internally arranged--gate by gate. Build the combinatorial logic to program the chip and match the signal names to the appropriate pins on the chip to replicate the 74LS2001 and you'd have a fully functional bus arbiter chip.

 

Still looking for that patent. Any keywords to pinpoint it?

 

I searched for Texas Instruments, Bus Arbiter and some variations.

 

The closest I got was this 1985 patent which describes a token-ring bus arbiter. https://www.freepatentsonline.com/4730268.pdf  It's still pretty cool. (I see more bus arbiter patents from 2000 onward.)

 

In #4730268 Distributed Bus Arbitration For A Multiprocessor System, a ring of (perhaps 4) arbiter chips will move a 1-bit access token around the ring in less than one clock cycle. Arbitration is achieved within one cycle.

 

A CPU can use the bus if it has the token, but afterward hands it to the next in the ring. Because of this, nobody gets starved out.

 

Potentially, no bus cycles are wasted: Another CPU can fetch or store while one CPU is doing an internal ALU cycle.  I think no CPUs need be put into a HOLD state, only single wait states. A CPU's bus drivers can be tri-stated until the arbiter grants access.

 

Contrast this with E-Bus, where priority is strictly ranked: a higher priority card gets access before a lower priority card. The lower priority card must complete its current operation, and get off the bus.

 

Share this post


Link to post
Share on other sites

There’s a lot of things that don’t make sense to me about E-Bus. 
 

I understand the arbitration sequence, but not how a 9900 could use it. CRU reads look like idle states, so nothing to trigger a bus request.  99105 has adequate information in the Bus Status codes. 
 

Timing is slow if BUSCLK is 3 MHz. The design guidelines indicate that higher speeds (limited to 10MHz) require a 4 layer backplane. 
 

It takes at least two rising  edges of BUSCLK before a bus access can begin. That’s two wait states added to every bus access (given 3MHz.) That’s before any waitstates for the memory. 

 

it’s a bigger disaster for the 99105 at 6MHz. To meet memory timing at 6MHz, the early read/write signal must get out to the bus, well, early. 
 

I imagined there would be a way for 2 equal CPUs to interleave access to the main bus, but I don’t see how that’s possible in an efficient way.  

 

More questions than answers. 


 

 

Share this post


Link to post
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

Loading...
Sign in to follow this  

  • Recently Browsing   0 members

    No registered users viewing this page.

×
×
  • Create New...