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FarmerPotato

LOAD vs RESET on 990 or TM990

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LREX/LOAD 

 

I’m curious how the Load Interrupt was used on the 990 or TM990. Also known as LOAD, NMI, and related to the use of the 9900 instruction LREX—Load and Restart Execution. 

 

*Bootstrap Loader*

 

I see many (all?) 990 had EPROM at FF00 or FC00. The FFFC load interrupt vector (unchangeable in EPROM) branches into code to  do some hardware “self-tests”, and then loads the OS from whatever tape or disk. 

 

Then I think I guess it called the RESET vector? (BLWP @0) I recall Dave Pitts put a disassembly of a ROM on his website, and that made it into Bitsavers.org. 

 

 

I think this makes sense for a logical separation of hardware initialization, loading the OS, whereas RESET can be a warm start. 

 

On the TI-99/4A, the RESET interrupt does initialization and starts the operating system, which we call GPL. 

 

THE 4A doesn’t rely on LOAD interrupt. It requires 32K RAM expansion anyway. So we use it for print screen or a debugger or game cheats. 

 

Also the 4A doesn’t implement any external instructions —LREX, IDLE, RSET, CLON, CKOF.)

 

*Single Step Hardware Debugger*

 

The 990/189 user manual or course workbook (I forget which) describes how to use LOAD to built a single-step function in hardware. 

 

That circuit raises NMI on IAQ, and I think it must be changed (right?) for CPUs that pre-fetch the next instruction, like 9995 and 99105. 

 

*Questions*

 

What did the RESET vector do on a 990 or TM990?

 

what kind of initialization did the 990 ROM do, that the RESET vector might assume already done? 

 

After bootstrap, how did the system enter the OS? Through the RESET vector (BLWP @0) or something else?

 

Was the LREX external instruction able to activate a hardware LOAD interrupt on any boards/computers? If so, was the RSET external instruction used for something different? 

 

990 users, can you share your insight into these areas?

 

*COLD*

 

In TI FORTH (4A version) the word COLD I think does BLWP @0 ( anything else? I think it locks up from not clearing user interrupts) 

 

I understood this as Cold Start. But from the point of view of the TMS9900 with LOAD, isn’t it really a Warm Start?

 

In TI 990 FORTH, what did COLD do? BLWP @FFFC for LOAD?

 

My Ideas 

 

I imagine using LOAD for bootstrap of a 99105 system. On power-up, there were would be EPROM at FC00-FFFE  (assume Flash EEPROM.) This ROM would bootstrap the executive BIOS, and then perhaps a choice of GPL or GeneveOS. 

 

 

Also, a BLWP @0 or even front panel button would warm  reset into GPL or whatever, not reboot the whole computer or reload the OS. (Instead Use the LOAD button for cold start from a lock-up.)

 

 

With PSEL active (engages the 99610 or memory mapper) the EPROM would disappear, and FC00 would default to paged  RAM. 

 

This would let user programs have FFFC for their purposes. It could still be configured as a single-step hardware debugger or print screen (Kudos to @Tursi and others who implemented software debounce on LOAD in the 4A.) . 

 

The front panel LOAD button would have to do some extra work to bring the EPROM back. 

 

I’m not entirely sure that this can be reconciled with front panel LOAD  and RESET buttons. 

 

I guess there is an answer in the 99000 data book where the flowcharts spell out what interrupts do. Most (all?) interrupts clear PSEL and PRIV status bits (while storing prior values in R15 to be restored by RTWP.)  If that’s true of LOAD, then it can’t be used to execute a vector in RAM. And the single step hardware debugger has to be integrated in the EPROM. 

 

I guess I want both a front panel LOAD button, and a distinct STEP button. 

 

The power up behavior would clear and raise LOAD, instead of RESET.  Typical circuit  is an RC discharged by the button, then charging up, plus a Schmitt-Trigger buffer LS14 to debounce and make a clean signal. 

 

On power-up, the 99105 emits a bus status code of Reset. I decode this (LS138) to generate a backplane RESET signal . This is called IORST in E-BUS. IORST is a more specific name that activates any RESET pins on backplane devices. 

 

Does the RSET instruction emit the Bus Status Code for Reset, or just the CRU bits indicating external instruction?

 

I know I could chase down these answers, but I only have a phone right now. And I’m interested in y’all’s perspectives. 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Well for the TM990 ...

 

You can configure the CPU board to generate either \RESET or \LOAD at power up, and select between memory maps that place the EPROM either at the bottom or top of memory (and RAM goes at the 'other' end). So you can configure it with EPROM high so you can set/modify the RESET, interrupt and XOP vectors (should you want to) as these would be in RAM, or configure it with EPROM low so you can set/modify the LOAD vector as this would be in RAM.

 

The RSET instruction is decoded to generate the \IORST signal.

 

The LREX instruction is decoded to do single stepping using the LOAD vector. [The same technique of single stepping using 3 cascaded flip-flops works with the 9995; the instruction prefetch doesn't appear to cause a problem.]

 

 

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