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bluejay

Any info about the pin headers inside the PET?

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So, the pin headers. I’m assuming it to be the system bus, but I’ve so far been able to find no info on what these are or the pinouts for them. They also seem to be a different shape for each major revision of the computer’s motherboard. Does anybody know anything about what they might be?

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I dont know if you would find it here or not... but it's worth a shot.

 

http://www.zimmers.net/anonftp/pub/cbm/schematics/computers/pet/2001/index.html

 

http://www.zimmers.net/anonftp/pub/cbm/schematics/computers/pet/2001N/index.html

 

 

The header strips in question are labeled J4 and J9.

320351-6.gif

 

The "Ram Expansion" schematics give a significant number of the pin numbers for these headers, and cite their signal line nomenclature.

 

320349-1.gif

 

 

are you considering the construction of a DIY SRAM expansion for a PET?

Edited by wierd_w
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This site has a more concise distillation of the above.

http://www.6502.org/users/andre/petindex/pinouts.html#memj4

 

Quote

 

8296 Memory expansion J4

MEMORY - EXPANSION
==================

Arrangement of pins  plug J4

+-----+-----------+-----+--------+
| PIN | SIGNAL    | PIN | SIGNAL |     J4
+-----+-----------+-----+--------+
|  1  | GND       | 26  | GND    | 25 o  o 50
|  2  | BD0       | 27  |  |     |    o  o
|  3  |   1       | 28  |  |     |    o  o
|  4  |   2       | 29  |  |     |    o  o
|  5  |   3       | 30  |  |     |    o  o
|  6  |   4       | 31  |  |     |    o  o
|  7  |   5       | 32  |  |     |    o  o
|  8  |   6       | 33  |  |     |    o  o
|  9  |   7       | 34  |  |     |    o  o
| 10  | N.C.      | 35  |  |     |    o  o
| 11  | N.C.      | 36  |  |     |    o  o
| 12  | /RAMSEL 9 | 37  |  |     |    o  o
| 13  | /RAMSEL A | 38  |  |     |    o  o
| 14  | /RAMON    | 39  |  |     |    o  o
| 15  | /SELEXP   | 40  |  |     |    o  o
| 16  | N.C.      | 41  |  |     |    o  o
| 17  | /CS 9     | 42  |  |     |    o  o
| 18  | /CS A     | 43  |  |     |    o  o
| 19  | /CS E     | 44  |  |     |    o  o
| 20  | /NOROM    | 45  |  |     |    o  o
| 21  | /PENSTRB  | 46  |  |     |    o  o
| 22  | /RESET    | 47  |  |     |    o  o
| 23  | READY     | 48  |  |     |    o  o
| 24  | /NMI      | 49  |  V     |    o  o
| 25  | GND       | 50  | GND    |  1 o  o 26
+-----+-----------+-----+--------+

8296 Memory expansion J9

MEMORY - EXPANSION
==================

Arrangement of pins  plug J9

+-----+-----------+-----+--------+
| PIN | SIGNAL    | PIN | SIGNAL |     J9
+-----+-----------+-----+--------+
|  1  | GND       | 26  | GND    | 25 o  o 50
|  2  | BA 0      | 27  |  |     |    o  o
|  3  |    1      | 28  |  |     |    o  o
|  4  |    2      | 29  |  |     |    o  o
|  5  |    3      | 30  |  |     |    o  o
|  6  |    4      | 31  |  |     |    o  o
|  7  |    5      | 32  |  |     |    o  o
|  8  |    6      | 33  |  |     |    o  o
|  9  |    7      | 34  |  |     |    o  o
| 10  |    8      | 35  |  |     |    o  o
| 11  |    9      | 36  |  |     |    o  o
| 12  |   10      | 37  |  |     |    o  o
| 13  |   11      | 38  |  |     |    o  o
| 14  |   12      | 39  |  |     |    o  o
| 15  |   13      | 40  |  |     |    o  o
| 16  |   14      | 41  |  |     |    o  o
| 17  |   15      | 42  |  |     |    o  o
| 18  | SYNC      | 43  |  |     |    o  o
| 19  | /IRQ      | 44  |  |     |    o  o
| 20  | DIAG      | 45  |  |     |    o  o
| 21  | PHI2      | 46  |  |     |    o  o
| 22  | B R/W     | 47  |  |     |    o  o
| 23  | /B R/W    | 48  |  |     |    o  o
| 24  | N.C       | 49  |  V     |    o  o
| 25  | GND       | 50  | GND    |  1 o  o 26
+-----+-----------+-----+--------+

 

 

So, it looks like that header really is just straight up for memory cards.  That's all Commodore intended to go there.

 

That doesn't mean you could not put a very carefully made expansion card on it-- it just means that the card would have to be memory mapped IO, and would be some custom arrangement that you define yourself, and then program for.  (Say for instance, using a mapper chip to segregate some small chunk of the very bottom of the RAM space, with a small ROM chip that contains the necessary service routines, and functions as a safe area of memory to use for "write on ROM" style bank switching (You use a combination of having the WE pin raised high, along with you chosen address pins, to temporarily disable the bus lines for the ROM chip, capture the written byte from the CPU on the write attempt and then hand that byte to the mapper chip, before re-enabling the data lines for the ROM chip before the next memory fetch cycle. Using a small chunk of such addresses, various 1 byte messages can be sent to your mapper chip, to control which bank and which "device" to enable in the mapped window), combined with a small tag of memory after that, which contains status register information and any additional signals needed for or about the memory mapped IO devices, which is currently mapped in via the mapper chip, etc. ) 

 

It would take multiple instruction cycles to work with such a solution (Have to write to the ROM address to select which "card" you want to talk to, burning one cycle-- then write to the status control register area to set any IO flags for that card, burning a second cycle, then finally write a single byte word to the card's memory mapped IO to tell it to do something, for the third. Best case scenario is that you avoid switching card contexts whenever possible, so that you can queue up several interactions with the currently selected card together, then switch contexts only as needed.  Alternatively, you could do something like TI did with their serial GROM chips, and simply have the bus automatically increment the currently activated card after access, thus getting one of the cycles back.), but it would work.

 

 

 

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@wierd_w I found those sites and schematics while researching on my own, but thought they wouldn’t be much use because they said 8296 on them. They’re completely different from 40xx PETs, aren’t they? 
 

I was thinking of building something a lot cooler than just a RAM expansion; a 65816 accelerator card or a Z80 card. I know the former has been done before using the CPU socket, but I wanted to know if the pin headers could be of much use. 

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