320k Parallel Port RAM Upgrade for 600XL & 800XL

[reifsnyderb]

12 minutes ago, ivop said:

Extracted the circuit for clarity.

 

NEU is German for NEW.

 

Just a wild guess, did you connect pin 9,10 and 11 to GND? With an LS part it shouldn't matter, but with a CMOS part it does. You need to pull down 6(C) and 7(R/C), too, with a CMOS part.

I used the 74LS123.  I don't remember if I pulled the unused "side" of the chip to ground or not.  (I doubt I did.)  I do remember reading in the datasheet about not pulling C and R/C to ground as I'd damage the chip.  The schematic I got was from post 13 of this thread:

 

 

I just looked at what you posted and the thread I posted.  Your post uses side "a" of the chip and I used side "b" of the chip as per the older post.  Otherwise, I connected everything correctly for side "b" of the chip.  Quite frankly, with all the references to this circuit I had a hard time believing it didn't work and spent extra time confirming everything.  My test results showed the output paralleling the phi2 input with a very tiny delay.

 

My quandary is since I wasn't able to get this 74LS123 circuit working that I don't want to make any assumptions, put it on a board, spend $50, wait 2 weeks, and find out it still doesn't work.

 

With all that said, I'd like nothing more than for someone to show me that I made a stupid mistake somewhere.

 

 

 

 

 

 

 

 

  

[reifsnyderb]

Here is the suspect part of the circuit.  I don't have the entire circuit here because it's hard to understand without zooming in on sections as I put the entire circuit on a single page in KiCad.

 

This is Revision 4.

 

In this revision I didn't realize I had so little time to store $D301 in the right-most 2 chips.  The 74LS74 and 74LS174 on the schematic.

 

/S6 comes down from another 74LS138 (not shown) which is set to work like the 800 obtains the select lines.  Doing it this way eliminates some chips.  So, /S6 really means A15 and A14 are high while A13 is low.  

 

Please keep in mind I have the chips listed as LS and usually reference them as LS chips but I really used F chips where possible.  However, if the timing isn't critical it really doesn't matter which chip is used.

 

Since the 6502 sets the address up when phi2 is low, there is plenty of time for the address circuitry to sort out the address.  So I don't see any place for a problem there.  However, I did run phi2 through an OR gate and I believe that was a big mistake due to the transition time of the OR gate.  In this circuit, when the address is correct and phi2 is low the output of the 74LS138 will be low going into the inverter of U42C.  So, when phi2 drops, U42C's output will go high so as to generate the pulse for the 74LS74 and 74LS174.  The 74LS74 stores bit 4 of $D301.  The 74LS174 stores bits 2, 3, 6, and 5 of $D301.  

 

If all the chips are F chips, with the exception of the inverter chip, the circuit works for a while....then eventually fails.  I can see banking, load SpartaDOS X, etc., etc.  If I change the inverter chip to an F chip the circuit doesn't work at all.  The datasheet for the 74LS74/74LS174 chips show there needs to be a larger transition time from low to high and I think that's the problem with using a 74F04 for the inverter.  Quite frankly, I think it's a weird conclusion I've drawn up but I can't find any other explanation and have determined everything else is not the problem.  So, my thought is to run Phi2 directly into the 74LS138 and eliminate the 74LS04 from this part of the circuit.  This brings me to what I am thinking may have a better chance of working.

 

I really suspect this circuit fails when an LS chip is used for the inverter because the exact same chip is also used for the SRAM chip select.  (Not shown in the schematics.)  I have verified that if I use a 74F04 for the inverter and disable the banking circuitry that I've got a stable 64k upgrade.

 

 

 

Here is my proposed Revision 5:

 

Here, I've routed Phi2 directly into the high enable of the 74LS138 and eliminated the inverter entirely.  As the address lines will have been set well before phi2 even rose, the only delay will then be the transition time of the 74LS138.  If a 74F138 chip works here I am positive there will be plenty of time to store the data lines after phi2 has fallen.  If I have to use a 74LS138 I am not as confident.  If I could have a shortened phi2 either of these circuits could work and it wouldn't matter if either LS chips or F chips are used.  But that adds another chip, a capacitor, and a resistor...not to mention I've had very bad success with the 74LS123.

 

 

I hope this all helps clear up the problem.

 

Thanks!

 

 

 

 

[ivop]

You are correct that even on a CMOS part C and R/C should not be pulled low. I was wrong there. Digital inputs to CMOS should never be floating, but analog pins can.

 

Are you sure that your LS123 is working properly? From my understanding it's the rising edge that triggers the trigger and the the length of the pulse depends on the R/C combination and not on whether the input is still high.

 

Edited June 13, 2022 by ivop

[reifsnyderb]

Just now, ivop said:

You are correct that even on a CMOS part C and R/C should not be pulled low. I was wrong there. Digital inputs to CMOS should never be floating, but analog pins can.

 

Are you sure that your LS123 is working properly? From my understanding it's the rising edge that triggers the trigger and the the length of the pulse depends on the R/C combination and not on whether the input is still high.

 

The 74LS123 that I used was brand new.  There is a possibility it was a bad chip and I didn't try another one.  However, the datasheet indicated that if you keep the pulse high the chip won't drop the output pulse early but will hold high.  The datasheet did not show any hint of an application of making a short pulse.

[ivop]

23 minutes ago, reifsnyderb said:

The 74LS123 that I used was brand new.  There is a possibility it was a bad chip and I didn't try another one.  However, the datasheet indicated that if you keep the pulse high the chip won't drop the output pulse early but will hold high.  The datasheet did not show any hint of an application of making a short pulse.

I might be wrong, but this datasheet seems to tell otherwise.

 

Triggered on transition. The basic output pulse width is determined by selection of an external resistor (Rx) and a Capacitor (Cx).

 

Sure your resistor and cap are correct? Not meant to belittle you, but it is really weird you cannot get the shortened pulse.

 

BTW if an R/C combination triggers a longer pulse, it is possible to indefinitely keep the output high if the input pulse is a clock.

 

 

74ls123.pdf

Edited June 13, 2022 by ivop

[reifsnyderb]

20 minutes ago, ivop said:

I might be wrong, but this datasheet seems to tell otherwise.

 

Triggered on transition. The basic output pulse width is determined by selection of an external resistor (Rx) and a Capacitor (Cx).

 

Sure your resistor and cap are correct? Not meant to belittle you, but it is really weird you cannot get the shortened pulse.

 

BTW if an R/C combination triggers a longer pulse, it is possible to indefinitely keep the output high if the input pulse is a clock.

 

 

74ls123.pdf 135.82 kB · 0 downloads

That's a nicer looking datasheet.

 

I was using this datasheet:  https://www.ti.com/lit/ds/symlink/sn74123.pdf?ts=1655147753421

 

Don't worry about belittling me.  If somebody could rub my nose in the problem to show me why this circuit didn't work for me I'd be grateful.  It's better to just admit I screwed up and move on.

 

The resistor and cap were correct.  I even changed them to see if anything changed and nothing changed.  

 

Looking at the datasheet it says on page 4, item 7:  "The retriggered pulse width is equal to the pulse width plus a delay time period."  Figure 5 seems to indicate that if the pulse stays high that the output will also stay high then add the delay time period.  So, from figure 5, I'd expect the 74LS123 to extend phi2, not shorten it.

 

However, I distinctly remember there wasn't a delay time period as per what this datasheet says there is.  But I checked, double-checked, and triple-checked all the connections.  I probably checked them again.

 

I suppose the brand new chip could have been bad.  I don't know.  I have another as I usually order 2 but since I had everything soldered to a small perf board and all the pins were soldered I didn't take the time to swap chips.

 

<sigh>  I'll have to breadboard it and try again I guess.  I distinctly remember spending a very long and extremely frustrating day trying to get the shortened phi2 pulse and having zero success.  Because of this, the 74LS123 left a very bad taste in my mouth, so to speak.

 

   

[ivop]

42 minutes ago, reifsnyderb said:

The retriggered pulse width is equal to the pulse width plus a delay time period.

That's the retriggered pulse width, i.e. when a second trigger comes in before the R/C output pulse is finished. Note that figure 5 does not show a third pulse. If that pulse would be there, and it would repeat, it would end up with a 100% duty cycle as mentioned on page 1.

 

Edit: which says: Retriggering to 100% duty cycle is possible by application of an input pulse train whose cycle time is shorter than the output cycle time such that a continuous "HIGH" logic state is maintained at the "Q" output.

Edited June 13, 2022 by ivop

[HiassofT]

With PHI2 connected to the CLR input (pin 3) the Q output should go low immediately after the falling edge of PHI2 - so Q shouldn't extend past PHI2.

 

With PHI2 connected to B (and CLR pulled high) the pulse with is determined only by R/C and can extend past PHI2 - you can use such a setup to control a latch to latch address lines beyond PHi2.

 

Either ways the pulse length is limited by R/C and it starts after some delay after the rising edge of PHi2. If the R/C time delay is small enough this can OFC be shorter than the PHI2 high duration.

 

The Nexperia (ex-NXP, ex-Philips) 74HCT123 datasheet contains some helpful information, including a chart with pulse with for small C values:

 

https://assets.nexperia.com/documents/data-sheet/74HC_HCT123.pdf

 

so long,

 

Hias

 

[reifsnyderb]

<sigh>

 

Well, I don't know why it didn't work before.  Maybe it was a bad day, a bad chip, or I had my head firmly planted up my rear end.  I suppose it could be a combination, too.   

 

It works.

 

Thanks for keeping on me about this.  I'll have to start incorporating it in my circuits when there is any concern about timing being an issue....such as memory banking on an XL or XE.

 

 

 

 

Phi2 on top and Phi2 Short on bottom.

 

 

 

[reifsnyderb]

Rendering of next board.  I was worried I'd have to re-do the entire board.  Fortunately, I figured out how to fit the 74LS123 on the same board by putting the power select jumper on the back side.  I checked both the 600xl and 800xl to make sure there's adequate clearance.  

 

 

[_The Doctor__]

now for a little puzzle, since it's 320K on the 600XL, is it 384k total on the 800XL, base plus add on card or?

I am just curious as to how the Total Ram for each system is shaking out and if any gets reclaimed for one or the other.

[reifsnyderb]

34 minutes ago, _The Doctor__ said:

now for a little puzzle, since it's 320K on the 600XL, is it 384k total on the 800XL, base plus add on card or?

I am just curious as to how the Total Ram for each system is shaking out and if any gets reclaimed for one or the other.

Nope.  It's 320k on either.  The internal RAM is disabled.  I didn't see a reason to complicate it more or to use the base RAM.  Actually, the chip used is a 512k SRAM chip.  But, since there are only 4 bits I can shadow at PORTB (2,3,5,6) the maximum extended memory is 256k.  Add in the 64k of base memory and that's 320k.

[_The Doctor__]

so you are completely disabling internal memory and providing 64 K base and 256 K both externally?

is that with or without ANTIC none/following/separated access. My assumption being without (none)

[reifsnyderb]

17 minutes ago, _The Doctor__ said:

so you are completely disabling internal memory and providing 64 K base and 256 K both externally?

is that with or without ANTIC none/following/separated access. My assumption being without (none)

It's CPU banking only as there isn't a /HALT line on the PBI...unfortunately.  I forgot to mention, as per the usual specifications, bit 4 turn on the banking by setting it to 0.

[ivop]

18 hours ago, reifsnyderb said:

<sigh>

 

Well, I don't know why it didn't work before.  Maybe it was a bad day, a bad chip, or I had my head firmly planted up my rear end.  I suppose it could be a combination, too.   

? I have to remember that expression.

 

18 hours ago, reifsnyderb said:

It works.

 

Thanks for keeping on me about this.  I'll have to start incorporating it in my circuits when there is any concern about timing being an issue....such as memory banking on an XL or XE.

Good to hear you got it working! Might be a defective LS123 you used the first time.

 

18 hours ago, reifsnyderb said:

Phi2 on top and Phi2 Short on bottom.

 

 

Nice scope! I only have a digital logic analyzer, so I did not see the amount of noise in the clock. Is that normal?

[+mytek]

1 hour ago, ivop said:

?

Nice scope! I only have a digital logic analyzer, so I did not see the amount of noise in the clock. Is that normal?

Probably depends on how close to the probe point the ground lead was connected. The farther away it is, the more noise will be displayed.

 

[reifsnyderb]

1 hour ago, ivop said:

? I have to remember that expression.

 

Good to hear you got it working! Might be a defective LS123 you used the first time.

 

Nice scope! I only have a digital logic analyzer, so I did not see the amount of noise in the clock. Is that normal?

When I measure the clock I have been seeing similar noise.  It could be as mytek said.

[+DrVenkman]

1 hour ago, reifsnyderb said:

When I measure the clock I have been seeing similar noise.  It could be as mytek said.

@mytek is probably right (as he usually is) - it looks like ground bounce/ringing. If you measure (for comparison) Phi2 directly off the legs of SALLY at pin 39, and Vss (ground) at pin 1, you should see a nearly-flat ground with little if any ringing. 

[reifsnyderb]

SUCCESS!!  I got the board in today and assembled it.  This board works.  The full 320k of RAM showed up right away and it ran on my 600XL without a problem.  SpartaDOSX worked fine with the extra memory and the installed RAMdisk was functional.  The 74LS123 did the trick.  SimChecker shows the 320k and banks, the RAM tests out, and most importantly it passes the M.U.L.E. test.  The 74LS123 is in the lower right corner.  Below it is a temporary 33pF capacitor as I came to the unfortunate realization that I don't have any surface mount capacitors of that size available and will have to order some.  Oh, yeah, I didn't bother cleaning the flux off yet.  lol

 

I'll test this out on the 800XL but I don't foresee any problems as it's just changing from internal power to external power via a USB-C connector and a jumper.  (The jumper is on the back of the board so as to make space for the LS123, and it's resistor and capacitor.

 

Once I get the surface mount capacitor in I'll keep this board on my 600XL.

 

 

 

Edited June 30, 2022 by reifsnyderb

[+mytek]

24 minutes ago, reifsnyderb said:

SUCCESS!!  I got the board in today and assembled it.  This board works.  The full 320k of RAM showed up right away and it ran on my 600XL without a problem. 

Looks very nice ?

 

Now all you need is a slick 3D printed case

 

[reifsnyderb]

2 minutes ago, mytek said:

Looks very nice ?

 

Now all you need is a slick 3D printed case

 

Thanks!  I do need to get my 3d printer back up and working.  It's been collecting dust on a table for over a year.  (I originally bought it to test out a 3d print head I built.)

[Frankie]

4 hours ago, reifsnyderb said:

 

 

How big is that?

[reifsnyderb]

6 minutes ago, Frankie said:

How big is that?

About 2" x 2.9" or about 51mm x 74mm.

 

[archeocomp]

We need this in Europe as well:-)

[+Larry]

Wonder if Ctirad, the guy who sold the Ram 320XL, still lurks here?  I hope this new version is successful.  Makes a very simple ram upgrade and coupled with a switchable OS, would give great user flexibility.  Truth be told, the disk-based translators do a good job, but flipping a switch is even better. 

 

@reifsnyderb, have you tested ram-under-rom software (like Turbo Basic XL) to make sure it still works?  I don't know why it wouldn't but it's easy to test.