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F18A


matthew180

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Another idea... but do as you like, it's just an idea: the F18A could offer a fast RND function, one write address to set the max value and one read address to get a random number between 0 and max. If your max doesn't change, just use the read value.

 

Yup, I thought about that, and I actually have that feature half implemented. Not sure if it will get finished though.

 

What about just some free-running LFSRs? The TMS9900 has a MPY instruction, so you can take the LFSR output and multiply it by the size of the range and take the upper bits of the result. That part doesn't need to be in F18A hardware. For additional entropy, you could XOR in whatever's currently on the data bus each cycle.

 

The update rule for the random number generator could then be as simple as:

 

   rng = (rng >> 1) ^ data_bus ^ (rng & 1 ? 0x8048 : 0);

 

(0x8048 is one polynomial I happen to have memorized. There's dozens out there, and all work pretty well.) With that running at the F18A's 100MHz clock rate, it'll be way more random than anything you'd hope to generate on the TMS9900.

 

 

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What about just some free-running LFSRs?

 

That's exactly what I was working on! Well, almost. I was not going to have it free running so you could set the seed and a have a reproducible list of pseudo random numbers if you need (good for debugging). Initially I was going to implement a Mersenne Twister (there is a free core available), but I didn't initially realize it requires 5 block RAMs, and I'm down to only 1 spare (the 16K chews up most of them, and the line buffers consume the rest). So, I started looking for a less resource intensive alternative and found the LFSR. I'll see what I can do about getting it worked in.

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That's exactly what I was working on! Well, almost. I was not going to have it free running so you could set the seed and a have a reproducible list of pseudo random numbers if you need (good for debugging). Initially I was going to implement a Mersenne Twister (there is a free core available), but I didn't initially realize it requires 5 block RAMs, and I'm down to only 1 spare (the 16K chews up most of them, and the line buffers consume the rest). So, I started looking for a less resource intensive alternative and found the LFSR. I'll see what I can do about getting it worked in.

 

Ah yes, reproducibility. That makes the random number generator WAAAY more complicated, since you need to know exactly how many times it's been read, and have well controlled ways of getting entropy into it.

 

In contrast, an actual random number generator wants to get entropy anywhere it can. It's practically the enemy of reproducibility.

 

If you want to enable a debug mode, why not just have an LSFR that only advances when read and can be reset to a known starting state with a write, and then the free-running thing with data-bus mixing for production purposes? Then it's just two different clocking modes.

 

The MT is just an LFSR on steroids with a huge delay line, anyway, if you look at what it actually does. :-)

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Ah yes, reproducibility. That makes the random number generator WAAAY more complicated, since you need to know exactly how many times it's been read, and have well controlled ways of getting entropy into it.

 

In contrast, an actual random number generator wants to get entropy anywhere it can. It's practically the enemy of reproducibility.

 

Or, a different thought: Just have two LSFRs. One that "free-runs" and one that advances when read. To debug your program just switch which one it uses. Switch it back once you're done debugging.

 

On a related note, CRCs are just LSFRs + an XOR on incoming data. If the one that advances purposefully let you write a byte (which would get XORed with the LSFR value) and then advanced 8 clocks, it would also double as a CRC accelerator.

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If I manage to get the feature added in time, it will definitely be LSFR based, probably 32-bit with xnor taps at 32, 22, 2, and 1 based on this paper:

 

http://www.xilinx.com/support/documentation/application_notes/xapp052.pdf

 

See pg. 5.

 

I will probably have a way to set the initial value, single increment, or free run. I will try to incorporate a divider so you can set a 0..n range for the result. I imagine being able to read 1 to 4 bytes of the result, and when you read the last byte it will single step to the next value, or start free running again (reading the 1st byte would stop the free running).

 

We'll see, but I still have a few other "base" features to get done, order boards, and put the suckers together.

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I think if you are going for a hardware random number generator, that reproducability need not be a design goal. A reproducable random number stream is not expensive to generate in software, but true randomness is very hard. Do existing hardware random number generators have reproducability? I thought they were free-running too.

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I'm really not sure, I never looked in to a hardware RNG, or at least I have never worked on a system that had one. Being able to set the seed, or set the RNG as free-running vs. stepped in the easy part. Implementing a range, which requires a hardware divide circuit, is the harder part. I have example HDL for both parts, I just have to get the time to bring them together.

 

So I'm getting the feeling that this would be a desirable feature?

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I'm really not sure, I never looked in to a hardware RNG, or at least I have never worked on a system that had one. Being able to set the seed, or set the RNG as free-running vs. stepped in the easy part. Implementing a range, which requires a hardware divide circuit, is the harder part. I have example HDL for both parts, I just have to get the time to bring them together.

 

So I'm getting the feeling that this would be a desirable feature?

 

Would a divide or a multiply be a better choice here? Multiplies tend to distribute any quantization bias a little more evenly. (PM me if you want more details.)

 

Since the TMS9900 at least has both instructions, do you need either? I guess the Z80 folks will feel left out if you didn't do the scaling for them. ;-)

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We have beaten on RNGs here: http://www.atariage....mber-generator/ and http://www.atariage....ly-rnd-routine/.

 

You pretty much want an RNG to produce exactly the same sequence from the same seed that runs through the given number range in as chaotic a way as possible and with as few duplications (preferably, none) as possible. This does, indeed, aid in testing because you can pick the seed. After testing, you usually add a step that starts with an unknown seed (usually by means of a function named RANDOMIZE), periodically, or for every call to the RNG to get closest to truly random numbers.

 

That said, there is a very good discussion on random number generation in Numerical Recipes, 3rd Edition by Press et al.

 

...lee

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Since I'm still undecided how I'm going to format my website with documentation, here is the v1.3 feature list. Some things might change slightly, but this is the bulk of it I think.

 

Main F18A V1.3 Features

 

Outputs standard 640x480@60Hz analogue VGA

Direct hardware pin-compatible replacement for the 9918A, 9928, and 9929 VDPs

Software compatible with the 9918A VDP

All four original 9918A graphics modes

80-column text mode

Per-tile color in text modes

Sixty-four programmable color registers with a selection from a palette of 4096 colors

Enhanced color modes for 2, 4, or 8 colors for tiles and sprites

Tile priority over sprites on a per-tile basis

Extra attribute information per tile: flip x, flip y, transparent, and palette select

Support for 30 rows in Graphics Mode I for an NES compatible display size (32x30 tiles)

Enhanced name table configurations to support scrolling

Horizontal and vertical scroll registers

Horizontal scan line interrupt

No per-line sprite limit, so all 32 sprites can be displayed on the same horizontal line

Sprite linking (move multiple sprites by updating a single sprite's coordinates)

Enhanced sprite collision detection information

Sprite size, 8x8 or 16x16, selectable per sprite

Extra attribute information per sprite: flip x, flip y

Address auto-increment selectable between +1 or +32 after a read or write

No CPU to VDP read or write speed limitations (up to 25MHz CPU clock speed)

 

 

Original 9918A Features Not Reproduced

 

External sync

External video input

Composite output

50Hz operation

4K VRAM addressing

Edited by matthew180
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UPDATE:

 

A week late, I know, I apologize. Since the minimum order to have the F18A manufactured was not met, I have decided I can handle the quantity myself and I will be doing all the assembly. This will slow down the delivery a little, but not too much I hope. Boards and parts have been ordered, and once they come in I will begin fulfilling the F18A orders in the order they were received.

 

Since the orders are not overwhelming, I'm going to leave the pre-orders active for now. I plan to make a few extra boards which will be on sale after the pre-ordres have been fulfilled, and beyond that I will consider making boards on an as-needed basis. My plan is to make the F18A available to everyone who wants one.

 

Thank you everyone for your support and patience, but the waiting is almost over! :-)

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UPDATE:

 

A week late, I know, I apologize. Since the minimum order to have the F18A manufactured was not met, I have decided I can handle the quantity myself and I will be doing all the assembly. This will slow down the delivery a little, but not too much I hope. Boards and parts have been ordered, and once they come in I will begin fulfilling the F18A orders in the order they were received.

 

Since the orders are not overwhelming, I'm going to leave the pre-orders active for now. I plan to make a few extra boards which will be on sale after the pre-ordres have been fulfilled, and beyond that I will consider making boards on an as-needed basis. My plan is to make the F18A available to everyone who wants one.

 

Thank you everyone for your support and patience, but the waiting is almost over! :-)

 

If you're looking for help, I'm happy to offer my board assembly and soldering skills to the effort.

Edited by Cory
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I'll see how it goes first, but I might just take you up on that. Thanks for the offer. By the way, did you ever get your disk controller working?

No, but I did isolate the problem down to a blown buffer. I just never got around to replacing it. The excitement was in the hunt for the problem. I still intend to replace it, but more exciting projects have taken its place.

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