Original SIDE cart hardware fixes.

[MEtalGuy66]

Im starting this thread to figure out how to fix CF card stability issues on the original "zaxxon built" SIDE cart.

 

 

So far, at Flashjazzcat's suggestion, I have installed additional supply/ground paths to the (U3)3.3v regulator. This did not seem to improve anything.

 

Additionally, I added a .1uF cap across the output of the regulator, and this did seem to reduce the frequency of the incidents I was noticing.

 

 

The problems I am noticing with modern CF cards involve the card "freezing" with the access LED on, and SDX reports either (138 Device does not respond) or (139 Device NAK). The only way to "unfreeze" the card is to power cycle the machine. This behavior seems to happen intermittantly and the frequency seems to increase with increased CF card access..

 

Candle has stated in the U1mb/SIDE2 thread that there was a JEDEC update that adressed some timing issues with SIDE, but that he is unsure what version of the JEDEC that ZAXXON actually used on the production carts. I was one of the first people to recieve my SIDE cart from ZAXXON.. Almost a year before most others were shipped.

 

There needs to be a path by which we can resolve these issues. Those who ordered/recieved the SIDE cart waited a LONG time in most cases and "kept the faith" even though ZAXXON was having serious issues. To have them working unreliably at this point is really sad...

 

Suggestions?

[candle]

due to zaxon doings regarding programming of these cpld chips, you might find that you need to replace it before reflashing it...

 

i have no words for this, as jed files are widely available, also for v2 devices...

[flashjazzcat]

What's the brand/size of card you're having issues with again Ken?

[MEtalGuy66]

It doesnt work right 100% with any cards.

 

I have (right here at the moment to test) cards ranging from 64meg to 8gig. Brands are iomega, sandisk, transcend, and monster digital (newest/fastest)..

 

Some times when you power-up the machine, it simply says "incompatible media".. Other times, it says "invalid partition table".. and yet other times, it mounts the APT partition fine, and then errors out (138 or 139) on access attempts.. and occasionally it will work right for a short period of time.. While some cards may work right more frequently than others, the erradic behavior does not seem to be exclusive to any one card.

 

If this is a CPLD programming issue, then the corrected JEDEC needs to be made available some place where people can easily get it.. And some links to whatever Xilinx tools are necessary would be nice too.

 

It's not Candle's fault that Zaxxon FUBARed this, but there needs to at least be support for those who can and are willing to fix the problem themselves.

Edited May 25, 2013 by MEtalGuy66

[+bob1200xl]

Is there a schematic for this somewhere? Source code?

 

Bob

[BillC]

Is there a schematic for this somewhere? Source code?

 

Bob

Information and schematics for most of Candle's projects are available on his website: spiflash.org. I found more info for SIDE at this page on his website.

[MEtalGuy66]

I noticed that on the side schematic, it specififies an XC9572XL-5VQ64C CPLD. This chip has a pin-to-pin delay of 5ns.

 

The chip that zaxxon used on my SIDE is clearly marked 10c, indicating a 10ns pin-to-pin delay.

 

 

Does this matter?

 

Digikey currently shows stocks of this one (10ns):

 

http://www.digikey.com/product-detail/en/XC9572XL-10VQG64C/122-1388-ND/826991

 

and this one (7ns):

 

http://www.digikey.com/product-detail/en/XC9572XL-7VQG64C/122-1450-ND/966631

 

Is either of these acceptible as a replacement?

Edited May 26, 2013 by MEtalGuy66

[AtariGeezer]

Mine is similar, but instead of F4200004A, mine shows F4197586A.

 

Is that dust or a solder bridge on the right side between pins 4-5 (top down) ?

[HiassofT]

I found more info for SIDE at this page on his website.

Looks like there's a JTAG connector (J2) at the bottom left of the PCB, so reprogramming the CPLD should be possible.

 

In order to do this, you have 2 possibilities:

 

#1: download the ISE WebPack (some 4-6GB) or ISE LabTools (still 1GB) from the xilinx website and use impact and a supported (xilinx) JTAG cable to program the .JED file.

 

#2: get someone (for example me to convert the .JED file into .SVF and use any JTAG programming cable / software to program the .SVF file (you might also need the BSDL files for the XC95XL series from the xilinx website).

 

I prefer option 2 and use urjtag and a Lattice parallel port JTAG cable to program my xilinx CPLDs.

 

To create an SVF file from the JED file you need impact from the xilinx software package. You can either do this by clicking around in the GUI (don't ask me for details, I don't use this method) or from the commandline:

impact -batch batchfile

 

where "batchfile" contains the following commands:

setMode -bs
setCable -port svf -file logic.svf
addDevice -p 1 -file logic.jed
Program -p 1 -e -v
Quit

 

Just drop me a line if you need some .jed file converted to svf.

 

so long,

 

Hias

[candle]

Hias, thing is, at least for these devices i had here at my place, that zaxon did put a lock on them, disabling any futher programming

 

and i really don't know what revision of jed file he has used

 

code (logic wise) didn't change, but pin drive strenght did, so line ringing was minimised

in v2 i've put additional resistors in series with suspected singals to damp the ringing even more, plus power path both to xilinx and cf card header were highly improoved

 

-10 chips are OK, -5 chips on schematics are just for pinout rather than actual BOM

[+bob1200xl]

Doesn't the security fuse just disable pre-load and verify? This would keep anyone from reading the JEDEC code from the chip, but not from doing a bulk erase. Once all the fuses were reset, including the security bits, you can then program the device again.

 

Bob

[MEtalGuy66]

Candle, you may also be interested in knowing this:

 

Last night I inspected my SIDE PCB under a microscope and found 2 pins on the XC9572XL and one pin on the LVC245 that were not soldered to the PCB at all. They were merely touching the gold plated pad on the PCB. I fixed them and this does not appear to have improved operation any, so I dont suspect it was causing a problem. However, this is obviously shit workmanship. And I would absolutely not reccomend buying anything else from Zaxxon or using him for any SMT assembly in the future.

Edited May 26, 2013 by MEtalGuy66

[HiassofT]

Doesn't the security fuse just disable pre-load and verify? This would keep anyone from reading the JEDEC code from the chip, but not from doing a bulk erase. Once all the fuses were reset, including the security bits, you can then program the device again.

Just checked the datasheet:

 

The CPLDs has read and write protection bits (page 14). If both of them are set, also erasing is inhibited. This suggests that we could be completely locked out.

 

OTOH, the same page says "Once set, the write-protection may be deactivated ... with a specific sequence of JTAG instructions".

 

The JTAG programming guide also mentions a "write protection override" setting in the impact erase options (page 3-14 / 39).

 

Maybe this could unlock the CPLD? Not too likely, but could be worth a try before replacing the chip...

 

so long,

 

Hias

[candle]

i've spent some time trying to figure out how to "override write protection"

but it comes down to the need of having special (not jtag) programmer for this purpose, so i'm out of luck

 

and in any case, why putting a lock on something one can legitymatly download right off my page?

[+bob1200xl]

Page 14 of the datasheet says the only way to reset Read Inhibit is to erase all the bits in the array. This is how I understand these CPLDs work.

 

Have you tried the ERASE command from the CLI? The -f option resets write-protect?

 

Bob

 

...regardless, the SIDE is a high density PCB with little opportunity for re-working much of the circuit. If you can't tweak the code, you won't have much chance to fix the SIDE. Is there any chance that damping resistors can be added to the IOR and IOW lines?

[atari8warez]

Im starting this thread to figure out how to fix CF card stability issues on the original "zaxxon built" SIDE cart.

 

 

So far, at Flashjazzcat's suggestion, I have installed additional supply/ground paths to the (U3)3.3v regulator. This did not seem to improve anything.

 

Additionally, I added a .1uF cap across the output of the regulator, and this did seem to reduce the frequency of the incidents I was noticing.

 

Try a 10uf tantalum cap on the output instead of 0.1uf.

Edited May 27, 2013 by atari8warez

[MEtalGuy66]

Ok.. So There are 7 signals that go directly from the CPLD to the CF.. What are we talking about? A 33ohm resistor in-line with each of them? I can do that by lifting pins at the CF card connector and inserting smt resistor packs or single smt resistors between the pins and the pads.

 

I notice that most cpld based CF card interface designs out there have these resisotrs in-line with the reset and i/o strobe signals..

Edited May 27, 2013 by MEtalGuy66

[+tf_hh]

Hi all,

 

my zaxon built-SIDE 1 has also had instability issues. I have done the Xilinx update with the latest code from Candle - and since them it works very well. Just built-in the header (in my SIDE there was a 2mm pitched 10-pin header of the left lower side, I´ve only to solder the header itself into the holes) and use Impact! of the Xilinx IDE. You can download Impact! seperately. The CPLD is protected, but with Impact! you can force to erase the whole CPLD - this also deletes all lockings.

 

Candle has put the JEDEC-file needed for reprogramming on his website: http://www.spiflash.org/atari/side/side-release.jed

 

Juergen

[HiassofT]

The CPLD is protected, but with Impact! you can force to erase the whole CPLD - this also deletes all lockings.

 

Candle has put the JEDEC-file needed for reprogramming on his website: http://www.spiflash....ide-release.jed

This is interesting, so maybe there's still some chance to get it working

 

I checked the impact manual and noticed that the "erase" batch command has a "override" option. So, by using erase/program/verify instead of program -e -v it should unlock the PLD

setMode -bs
setCable -port svf -file side-release.svf
addDevice -p 1 -file side-release.jed
erase -o -p 1
program -p 1
verify -p 1
quit

 

I created SVF (ascii) and XSVF (binary) files with these settings from the JED above, so anyone with a (X)SVF capable JTAG programmer can give it a try (I don't own a SIDE cart).

 

so long,

 

Hias

side-release-svf.zip

[candle]

can anyone check it with Andreas (CharlieChaplin) side?

[+bob1200xl]

The IOR and IOW lines are edge-triggered so any ringing on them will give you two reads or two writes instead of one. These are the two signals that need to be clean. I don't know about RESET. You can reset the card from the secondary interface in software.

 

330 ohms is way too high - 50 to 100 ohms (47, 56, 68, 75, 82, 91, 100) seems to work best on a 5 volt interface.

 

It sounds like a code change will do the job, however.

 

Bob

 

 

 

 

 

Ok.. So There are 7 signals that go directly from the CPLD to the CF.. What are we talking about? A 33ohm resistor in-line with each of them? I can do that by lifting pins at the CF card connector and inserting smt resistor packs or single smt resistors between the pins and the pads.

 

I notice that most cpld based CF card interface designs out there have these resisotrs in-line with the reset and i/o strobe signals..

[+tf_hh]

can anyone check it with Andreas (CharlieChaplin) side?

I contact him directly.

[MEtalGuy66]

The IOR and IOW lines are edge-triggered so any ringing on them will give you two reads or two writes instead of one. These are the two signals that need to be clean. I don't know about RESET. You can reset the card from the secondary interface in software.

 

330 ohms is way too high - 50 to 100 ohms (47, 56, 68, 75, 82, 91, 100) seems to work best on a 5 volt interface.

 

It sounds like a code change will do the job, however.

 

Bob

 

Thanks, Bob. I had forgotten that you had done all that work with CF cards on the atari in the past.

 

btw, I said 33, not 330..

 

Yeah most "reference" design schematics I have seen where a cpld is driving those signals directly have these "dampning resistors" in line with those signals.

[HiassofT]

The IOR and IOW lines are edge-triggered so any ringing on them will give you two reads or two writes instead of one. These are the two signals that need to be clean. I don't know about RESET. You can reset the card from the secondary interface in software.

 

330 ohms is way too high - 50 to 100 ohms (47, 56, 68, 75, 82, 91, 100) seems to work best on a 5 volt interface.

Page 29 (47 in the PDF) of the ATA-8 parallel transport draft lists the series termination resistors required for Ultra DMA:

 

22 ohms for IOR and IOW, 33 ohms for CS, A0-A2, D0-D15 and reset.

 

so long,

 

Hias

[+bob1200xl]

I have seen those values suggested. I actually measured the ringing with a very fast scope and came up with somewhat higher optimum values. It all depends on the logic family (CMOS 5v, TTL 5v, etc.). On a 74HC138 driver, I used 75 ohms. An Atmel 750 CPLD actually works well with no resistors, but I put 47 ohms in them anyway.

 

There are many ways noise can get to you. The faster the clocks, the worse it is. I can't get an SDHC card/adaptor to work at all.

 

Bob