Complete documentation of Pokey serial modes - SKCTRL

[thorfdbg]

Hi folks,

 

just wondering whether there is anywhere a more complete description of the POKEY serial modes. SKCTL is found in the official Atari specs, but the table listed there is, at best, "misleading" if not confusing. For example, combination 110 is there listed as "In-rate" coming from channel 2, though the "comments" column lists that the receive rate is coming from channel 4. Furthermore, and even more confusing, it seems that pokey in this mode uses channel #4 as output for the clock line, though channel #2 is used to drive the data-out (huh? why is that useful?)

 

Also, the document sometimes states "chan 4" or "chan 3&4". Probably the intention was to say, "well it is actually driven by channel 4, but for useful baud rates, you should probably link channels 3&4". I would be astonished if channel linkage for serial output would be independent from AUDCTRL.

 

Thus, instead of this table, it would probably be more useful what the individual bits switch between.

 

Let me see what I understand from this table:

 

In mode 000, input and output are synchronized to the external clocks, no channels used.

 

In mode 001, the transmission rate is synchronized to the external clock, though the receive rate is unsynchronized and linked to channel 4.

 

In mode 010, the transmission and receive rates are unsynchronized and linked to channel 4, and channel 4 is output on the clock.

 

In mode 011, channel 4 is used to define the input and output clocks, which are unsynchronized, though the clock line is used as input (for what?). The mode is "not useful". Why is that so? It depends on what the clock input is supposed to do.

 

In mode 100, the transmission rate is defined by channel 4 and not output (thus, this is actually an asynchronous mode, despite what the table says?) and input is clocked by the clock pin (synchronous mode). This seems to be the inverse of mode 001.

 

In mode 101, output rate is clocked by channel 4, and input is clocked by 4 as well, though the clock line is an input as well. Question is what this input does, then. Again, specified as "not useful".

 

Mode 110 sets the output rateby channel 2, and - if I believe column 6, input comes from channel 2 as well. This is probably a typo and should say that input comes from 4? Channel 4 is used to drive the clock. Thus, in this mode, pokey drives an external device how it should clock its data to make pokey receive it, unlike the modes before where pokey was listening to the clock line, or was finding the synchronization itself due to the stop bits.

 

Mode 111 sets the output rate to channel two, but does not output the clock, and the receive rate to channel 4. Input is not synchronized.

 

Do devices on the SIO bus actually use the clock? They could use the output clock in mode 010, though probably don't. Apparently, SIO communications does not expect an external clock.

 

 

[foft]

I found the fold out pokey diagram in the hardware reference manual helpful for explaining these since you can see the high level with the logic gates for this, but its not THAT clear to me either...

 

I think this one is probably the source if you want accurate info: http://atariage.com/forums/topic/182670-pokey-decap/ :-)

 

Also Avery discusses these in his Altirra hardware ref manual but I guess you've read that.

 

edit: I came up with this in my pokey impl - but pretty sure some are wrong!

	-- serial clocks
	process(sio_clock,skctl_reg,clock_reg,clock_sync_reg,audf1_pulse,audf2_pulse,audf3_pulse)
	begin
		clock_next <= sio_clock;
		clock_sync_next <= clock_reg;
	
		serout_enable <= '0';
		serin_enable <= '0';
		clock_input <= '1'; -- when output, outputs channel 4
		
		case skctl_reg(6 downto 4) is
			when "000" =>
				serin_enable <= not(clock_sync_reg) and clock_reg;
				serout_enable <= not(clock_sync_reg) and clock_reg;
			when "001" =>
				serin_enable <= audf3_pulse;
				serout_enable <= not(clock_sync_reg) and clock_reg;
			when "010" =>
				serin_enable <= audf3_pulse;
				serout_enable <= audf3_pulse;
				clock_input <= '0';
			when "011" =>
				serin_enable <= audf3_pulse;
				serout_enable <= audf3_pulse;
			when "100" =>
				serin_enable <= not(clock_sync_reg) and clock_reg;
				serout_enable <= audf3_pulse;
			when "101" =>
				serin_enable <= audf3_pulse;
				serout_enable <= audf3_pulse;
			when "110" =>
				serin_enable <= audf3_pulse;
				serout_enable <= audf1_pulse;
				clock_input <= '0';
			when "111" =>			
				serin_enable <= audf3_pulse;
				serout_enable <= audf1_pulse;
		end case;
	end process;

+async/sync

		-- resync clock on receipt of start bit
		if ((skctl_reg(4) and sio_in_reg and waiting_for_start_bit)= '1') then
			async_serial_reset <= '1';
			serin_clock_next <= '1';
		end if;

Edited March 16, 2014 by foft

[phaeron]

Most of the serial port works exclusively with channels 2 and 4, and thus channels 1 and 3 are only involved if linked with 2/4. However, there are two important cases where channels 1 and 3 are involved directly. If two-tone mode is active, channels 1+2 get reset together, and if asynchronous receive mode is active, channels 3+4 get reset together. This is independent of whether they are linked.

 

The hardware manual has a mistake in its chart for the 110 setting. Channel 4 is the receive clock in that case. I assume the reason that modes 011 and 101 are specified as not useful is that they have no utility over modes 010 and 111. If you're doing output, having the output clock in asynchronous input mode is useless.

 

I think some MIDI adapters may have piped the 31KHz MIDI clock into the external clock input.