I'm hoping if/when there's a jailbreak firmware it'll at least include the chips that are currently simulated on the SD2SNES, even if the different chips have to be shuffled off to a "second" SNES core, like is done with some of the mappers on the NT Mini NES core. SA1 and SuperFX jailbreak support would be amazing, but I understand it may not be possible. This brings to mind 2 questions I've been thinking about regarding the Super NT for awhile now:
1. For SA-1 and SuperFX, would it be possible to use a real cartridge equipped with these chips as a "donor cart", so to speak, to just use the real chips for processing, but load the rom from the internal "rom cart" on the FPGA? I assume this would be impossible if there is any interface between SA1 or SuperFX and the ROM on the cartridge, but i would think it would be feasible if the chips only interfaced with system RAM.
2. Assume unlimited FPGA space and the successful reverse engineering and implementation of all of the SNES enhancement chips onto a single FPGA core. Could some kind of crazy homebrew be written that could use all of the expansion chips?
1. Donor carts, No it wouldn't be directly possible because of where the chip exists in the cart. The Mask ROM, and SRAM are always connected. At least two pinout maps out there suggest that the south end of the SA1 chip connects to the SNES bus and the north end connects to the MASK ROM along the same bus. The problem I see is that even if the ROM/SRAM is prevented from being accessed by the FPGA CPU, there is nothing stopping the SA1 from accessing it. The most likely scenario here is really to have the SD2SNES or some other flashcart emulate the chip alone if additional FPGA power is needed. But it's likely that all the chips could be emulated by the NT Mini, just not all at the same time (and that's an unlikely configuration.) So you might have to switch between "SNES+SFX","SNES+DSP's","SNES+SA1" modes or something in the same way you'd switch between a GB, SGB, GBC.
2. In theory yes, for practical reasons, unlikely.
The SuperFX chip is a RISC CPU that acts like a GPU in modern contexts. In theory you could "overclock" it.
The Cx4 chip is a DSP by Capcom
DSP1-4 are DSP's by Nintendo
S-DD1 is basically a hardware image decompression chip
S-RTC is a real time clock
SA-1 is a faster 5A22 that acts in parallel with the system CPU, hence this requires roughly the same amount of FPGA space as the main CPU
SPC7110 is another image decompression chip plus a RTC
ST010,011 and 018 are all CPU's used for AI in games, of which the latter two are only used in Shogi titles, and the 018 is out of reach for a FPGA, having CPU power closer to that of the GBA.
If you could access all of them at the same time, you'd jam up the expansion bus, and it's likely that something like the SA-1 and SuperFX would never be able to communicate with each other.
Between the SNES and the Amiga, both systems essentially were early attempts at separating the subsystems to make use of parallelism and waste less bus bandwidth. Where as on the PC at the time, absolutely everything went over a single bus, and manual configuration of addresses and IRQ's were needed. There was no parallelism. If you stuck something like a RAM expansion board into an ISA slot, during the memory test you'd get the onboard memory to test at normal speed, but as soon as it hit the expansion board it would be slowed down to the expansion bus speed, a bus that was shared with the video, sound and other things. I imagine on the SNES, if it were possible to stick something like the SuperFX and the S-DD1 on the same bus, you'd have to use the main CPU to pass data between them, thus slowing the bus bandwidth in half.
In theory though, it's a FPGA, you could probably overclock all the chips and the bus. But you'd never be able to get a game to work on to different versions of the JB firmware, let alone any software emulators in order to debug it.