ANTIC REF (Refresh) output.....is it any use ?

[Rybags]

They couldn't change Ref behaviour as in reducing number of cycles - it would have broken so much software with the benefit of a miniscule performance increase.

 

I suspect that if removed there'd be no noticable effect on most machines. If it is the case that A0-A7 is row select then the problem of Ram under active Rom not being refreshed shouldn't be possible (though I have doubts about the 800).

Edited November 22, 2017 by Rybags

[HiassofT]

The main purpose of the ANTIC refresh signal in the Atari computer is to make refresh cycles distinguishable from "real" ANTIC access cycles and thus preventing memory and peripheral chips from reacting on refresh and driving the data bus.

 

When refresh is asserted the MMU will assert the cas-inhibit signal and deassert IO, BASIC, OS and cart (S4/S5) signals. PBI devices should do the same, when refresh is asserted they should simply ignore the current cycle and keep the databus tristated.

 

On the bus a refresh cycle looks like any other antic cycle. RW is 1 and Antic drives the address lines. A0-A6/A7 are incremented on each refresh cycle and A8-A15 are set to 1 - but I'm not sure if the latter is actually specced somewhere.

 

So, a refresh cycle usually looks like a normal $FFxx access - only difference to a normal RAM/ROM read access to this address is that the refresh signal is asserted.

 

As each memory access cycle (also those to IO, ROM etc) drives the DRAM RAS signal DRAM rows are refreshed on ROM etc accesses as well. If you want to provoke refresh errors, eg when using an old ANTIC with 64kbit DRAMs you have to make sure no such access will happen. i.e. turn off antic DMA, interrupts and keep a small loop running for a few seconds in a memory area that doesn't change A7. I don't have any of these old ANTICs so I'm not sure if it'll drive A7 to low or high on refresh. So test both with a loop in $xx00-$xx7f and $xx80-$xxff.

 

so long,

 

Hias

[ijor]

The newer DRam types have the refresh pin but as mentioned, those chips support both types of refresh and Atari only uses Ras-only regardless.

 

Really? Exactly which ones? I don't see this. Newer chips have an auto refresh mode but no refresh pin, auto refresh is usually enabled with a CBR (CAS before RAS) cycle.

 

From my o-scope measurements I seem to remember that REF is faster on the newer ANTIC than on the older, which , with my limited knowledge, feels strange as you would expect newer types (single voltage) of memory to need less refresh cycles.

...

Apart from that i wonder if any of the RAM test programs would notice if I would lift out the REF pin out of the socket....

By REF being faster in newer ANTIC, you mean at a higher frequency? No. That can't happen as that would reduce the number of available cycles and would break some software.

 

As you can see from what was mentioned earlier, disconnecting REF is (almost) completely harmless. DRAM would still refresh anyway.

 

The main purpose of the ANTIC refresh signal in the Atari computer is to make refresh cycles distinguishable from "real" ANTIC access cycles and thus preventing memory and peripheral chips from reacting on refresh and driving the data bus.

 

When refresh is asserted the MMU will assert the cas-inhibit signal and deassert IO, BASIC, OS and cart (S4/S5) signals. PBI devices should do the same, when refresh is asserted they should simply ignore the current cycle and keep the databus tristated.

IMHO, main REF purpose was probably just in case it could be needed in the future, or otherwise it was a bit of an over engineering. In the actual implementation it is completely harmless if the databus is driven and no tristated. If they really cared about any chip reacting on the address (any device performing some kind of strobe even on a read cycle), they could have grounded a couple (or even all) the higher address lines on refresh cycles. That would have been cheaper than the logic required for REF.

 

A0-A6/A7 are incremented on each refresh cycle and A8-A15 are set to 1 - but I'm not sure if the latter is actually specced somewhere.

...

I don't have any of these old ANTICs so I'm not sure if it'll drive A7 to low or high on refresh.

 

On ANTIC rev E, the unused address signals are high as a consequence of the internal address bus being open drain with a precharge. The refresh counter is not connected to the highermost signals. More than likely it is the same on the older revision.

[Rybags]

Mistake in that post earlier... I should have said the newer chips have provision for automatic refresh, not an actual pin to do it.

 

Looking at a couple of datasheets - a 4416 has 8 address pins for 8 rows * 6 columns and 128 refresh cycles each 2 ms.

A 41464 has 256 refresh cycles in a 4 ms period.

 

2 ms is about 31 scanlines in PAL which equates to 279 refresh cycles. In a normal 40x25 with badlines situation we might lose 45 of those giving 234.

So, in a "normal worst case" situation the Atari is generating just under double the required number of refresh cycles for those particular DRams.

 

The C64 with 5 refreshes per scanline would give 155 which is about 20% more than required.