H/W question: interrupt synchronisation on 99xx/99xxx

[pnr]

In several 99xxx designs (for example this one: http://www.itech.net.au/tms9900/downloads/tms99105a_sbc.pdf) I see the interrupt lines being latched on the rising edge of CLKOUT. I wonder if this is necessary.

 

Neither the 9900 or the 99xxx data manuals specify that interrupt sources must be synchronised. The 9900 manual says that the interrupt inputs are monitored continuously (but presumably in particular during clock phase 4) and the example external circuit does not have a synchronising latch. The 99xxx manual says that the interrupt inputs are sampled on the falling edge of CLKOUT; here there is no example circuit.

 

However, the design handbook "The 99000 microprocessor - Architecture, software and interface techniques" does claim that inputs must be latched at the rising edge of CLKOUT before being fed into the priority encoder (74LS148 etc.), and the example circuits all have such synchronisation.

 

The only reason I can see for such synchronisation is that it avoids a bad interrupt level being read if the priority encoder is changing state just at the time of the falling CLKOUT edge (e.g. interrupt #2 being out-prioritised by interrupt #1 and the encoder giving a transient result suggesting a #3 interrupt was present). This condition is more simply (and cheaply) handled in software, imho.

 

Does anybody see another reason?

 

 

[matthew180]

If the 99xxx uses level-triggered interrupts like the 9900, then synchronization to the CPU clock (particularly a phase other than the phase used by the CPU to sample the interrupts lines) would be highly recommended. I guarantee if you do not synchronize, you will get spurious interrupts.

[Stuart]

Looks like the TI documentation is inconsistent with regards what's required. There's an example diagram in the 9900 data manual (as you say) with a pair of cascaded 74148's with no synchronisation. The 74148 was also sold as the TIM9907, and looking on the page for that in the Microsystems Designers handbook there's an application diagram showing a 74148 connected to a 9900, and preceded by a LS373 latch clocked by phase 3 clock. Right beside it there's a 74148 connected to a 9980/9981 with no latch. If you're using a 9901, then they are latched in that.