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To infinity and beyond... (new hardware)


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#126 Kyle22 ONLINE  

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Posted Sun Sep 23, 2018 4:50 PM

That is usually done to create equal length signal paths so the signals arrive at precisely the right time.



#127 _The Doctor__ ONLINE  

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Posted Sun Sep 23, 2018 4:52 PM

they aren't saw tooth but rounded,

this is done to defeat skewing of the inputs, so they are of the same length... there are a multitude of benefits, but you have got to be careful because they can become antennas... this technique when done correctly assures timing will stay spot on amongst other things..

 

oh sure kyle, you wanted to beat me to it...  :)    here are some links to further the broader picture and multiple reasons... pro and con...

 

https://electronics....aped-pcb-traces

http://www.ultracad....nal timing2.pdf

 

fun stuff.


Edited by _The Doctor__, Sun Sep 23, 2018 4:55 PM.


#128 Osgeld OFFLINE  

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Posted Sun Sep 23, 2018 5:39 PM

 

Still here ? Zoom in, I dare you :)

 

 

 

90 degree trace turns, kind of wish I didnt zoom in 

 

at a 10,000 foot level signal wise they are bad in part due to eddy currents, production wise (if one was to start making thousands of these things) the corners have a great chance of peeling up 

 

on a personal note, I would have put teardrops on those super tiny traces going to though hole parts and the inset route of the PCB under the SD card will have rounded internal corners, I doubt it matters much in this situation but I have pointed that out to other people where they are making a cart board (for instance) to fit in a shell and its not going to work putting square plastic in oval slots :)

 

I dunno how mission critical my above comments are (and I assume you will have planes) just my brain twitching into "we will make 450,000 of these and feed them to robots" mode

 

cid-logo.jpg


Edited by Osgeld, Sun Sep 23, 2018 5:45 PM.


#129 Spaced Cowboy OFFLINE  

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Posted Sun Sep 23, 2018 6:24 PM

It looks fantastic! All the serpentine routing indeed makes your brain hurt ;)

 

May I ask, which software do you use?

 

All the design work is done in Eagle - I've been using it now for about a decade and even though it has its foibles, I'm used to them by now. 

 

Generally I route "important" signals by hand - things like power planes, power entry, differential pairs, clocks and busses and then let the autorouter take over and do "the rest". On this project, however, I started to hit a serious wall where the autorouter would take ~8 hours or so just to get to a position where it couldn't route any more traces, and there were still dozens to go. Finishing off an autorouters's job isn't a fun task... The main problem is that Eagle's autorouter is a grid-based autorouter, so to get high-resolution routing across a large board, it has an enormous problem-space to solve. So I started to look elsewhere. I asked around at work and they all use Specctra (which of course is licensed in the tens of thousands of dollars per seat per year) so that wasn't a go. There is however an autorouter that is very similar in design to Specctra, called Electra. The interface isn't as slick as Specctra, and I've been working through some rough edges with the developers with the Eagle integration (who've been excellently responsive, by the way) but it's a fixed-cost per permanent licence. My usual boards are 4-layer, but this needs 6, so they came up with a halfway-house between the "total pro" and "semi-pro" that had the 6 layers but didn't include auto-routing of high-speed differential pairs. After a month or so of testing, feedback, and updates I went for the Pro-6L option.

 

Electra is not grid-based, it's shape-based, so it only takes about 10-15 minutes to run a full autoroute, with high-speed serpentine routing based on net-classes, and it's scriptable, so I write a ".do" file that decides how the autorouter will behave...

unit mm
bestsave on
rule pcb (width 0.101600)
rule pcb (clearance 0.101600)
rule pcb (clearance 0.304800 (type via_area))
rule pcb (clearance 0.101600 (type wire_smd))
rule pcb (clearance 0.304800 (type wire_area))
bus diagonal
fanout 5

circuit class sdram (match_net_length on 10)
circuit class sdram (length 100 90)

circuit class lcd (match_net_length on 10)
circuit class lcd (length 100 80)

circuit class cclk50 (match_net_length on)
circuit class cclk50 (length 80 60)

circuit class qspi (match_net_length on)
circuit class qspi (length 20 15)

circuit class xspi5 (match_net_length on)
circuit class xspi5 (length 90 80)

circuit class xspi6 (match_net_length on)
circuit class xspi6 (length 110 100)

select class clock
route 10
protect selected


select all nets
route 20
clean 2
route 25 16
clean 2

filter 5
recorner diagonal
unit inch
recorner diagonal 1 1 1
recorner diagonal .1 .1 .1
recorner diagonal .006 .006 .006
recorner diagonal .003 .003 .003
gloss

report status
unprotect all wires
write script {xio2.scr}

(I'm still learning this, I'm sure there's still lots to explore - you can set up "fences" for the router so that classes of nets are routed only within that fence, for example)

 

... and tell it to have at it. A while later, I have a file "xio2.scr" that I can run from within Eagle, and it will create Eagle equivalent of the autorouter model.

 

Anyway, I think Electra's great. I love the results it gives, and that it's not subscription based. It's a big cost straight-up for me, but I can use it in its current form from now on, and the support is fantastic.

 

 

Yeah, I'm curious what the point of all the saw-tooth routing is about.  I could make some wild guesses, but I'd most likely be wrong.

 

 

So, when you've got a signal running at 100 MHz, you have a finite time within which you can recognize the signal as high or low before the next bit comes along (about 10ns at 100MHz in fact). Within any given 10 nanoseconds, there will be a fraction of it called the setup time, and a fraction of it called the hold time, thus:

 

58_1186817796.gif

 

generally centered around a clock signal, so you basically want to make sure that all the data line values are in-place and steady within that time period of the 'setup time', then the clock transitions from high to low (or vice versa), and they have to remain steady for the 'hold time'. All well and good.

 

Here's the catch: It takes the electrical signal a certain time to travel down the wire, so if you have (like I have for example) 32 different data lines, 15 address signals, and various other signals (clock-enable, read/write, row-address strobe, column address-strobe etc.) then it's important that *all* these signals arrive such that they satisfy the setup and hold times for the chip at each end.

 

The only real way to control this is to make the lengths of each signal very similar (they don't have to be identical, there's a range of time over which it'll all work) but this is complicated by the fact that the pins on each chip (in my case the STM32H7 and the SDRAM chip) are all in physically different locations (for obvious reasons) so the distance between them is already different for each signal, and the density of the pin layout means that some signals will be naively routed far and away from all the others, just to *make* the connection, let alone make it under any constraint.

 

So you end up with a lot of signals that need to be extended in some way in order to make their path longer, because you have to route some signals over long paths, and you can't make the distance for some signals be too different from the distance for other signals - hence the serpentine routing.

 

For what it's worth, the EE team at work recommended that I try to achieve 0.5% of a wavelength as the maximum disparity between signals on the same bus. At 100 MHz, the wavelength is ~3m (meters), so 0.5% of that is 1.5cm. That's actually a surprisingly tough target. When challenged, there was the typical "suck air in between teeth, shake head, and say "well, I don't know, if I were you I'd stick to that" response :) )

 

Currently, out of 43 signals, I have 4 where the largest disparity from CLK is not hitting that target, so there's still a little work to do. The two largest busses are the VGA (actually the LTDC bus) and the SDRAM; I intend to relax the VGA constraints a lot to help the SDRAM hit their target - it's far more important that the SDRAM has no data-errors than a pixel on the VGA is momentarily very slightly different ...



#130 Spaced Cowboy OFFLINE  

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Posted Sun Sep 23, 2018 6:33 PM

90 degree trace turns, kind of wish I didnt zoom in 
 
at a 10,000 foot level signal wise they are bad in part due to eddy currents, production wise (if one was to start making thousands of these things) the corners have a great chance of peeling up 
 
on a personal note, I would have put teardrops on those super tiny traces going to though hole parts and the inset route of the PCB under the SD card will have rounded internal corners, I doubt it matters much in this situation but I have pointed that out to other people where they are making a cart board (for instance) to fit in a shell and its not going to work putting square plastic in oval slots :)
 
I dunno how mission critical my above comments are (and I assume you will have planes) just my brain twitching into "we will make 450,000 of these and feed them to robots" mode
 
attachicon.gifcid-logo.jpg


Well, I'm sure being a member of the PCB designer's council you'll have a lot more knowledge about this than I - I'm just a software guy and I'm certainly willing to be educated if I'm wrong, but I was under the impression that 90-degree cornering was more of a religious thing than actually having any practical impact, especially at the frequencies we're talking about (top-end of 100 MHz). There's several places on the 'net that basically debunk the whole idea based on experimental data measurements (see http://www.thehighspeeddesignbook.com, chapter 25, for example).

 

Teardrops are a good idea, thanks :) I'll have to see if I can tease those out of Eagle somehow - actually apparently there's an ULP called teardrops.ulp which will do just that. The inset I'm not bothered about, it's only there to aid removal when pulling the card out with a finger.

 

As for run numbers, well, currently the projected run is ... 5. Just 5. If all goes well, and those 5 perform acceptably, then the next run will be much larger, maybe 50, with different people getting them based on demand. If things go unbelievably well, then there may be *another* run of 50. Or not.

 

And yes, there's a full ground plane, a full power plane, a mixed signal/power plane (where the power is point-to-point and of different voltage) and then there's another 3 signal planes.



#131 Osgeld OFFLINE  

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Posted Sun Sep 23, 2018 7:17 PM

the biggest practical inpact I have seen is in really high frequencies like ghz range, high power applications (which this is not) and board production quality, as in traces shorted cause it didnt fully etch the inside corner, that has actually bit me once at a tune of about 8 grand (not my money of course heh) 



#132 _The Doctor__ ONLINE  

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Posted Sun Sep 23, 2018 7:46 PM

um finish line needs exacto knives and repair mask? runs and hides.  :o

I am not a fan of right angle traces in all honesty. The nature of electrons and the field generated by them in nature do not like it, rounded 90 degree elbows are nice and don't hurt the field or flow so much. Kind of strange how it all starts to looks like wave guides at some point in my head...

 

now what gets crazy is real world testing... bend wire at super sharp 90 degrees and is gets more resistive... but form the metal with the 90 degree angle in it and it doesn't... the bent metal is spread apart as it is stressed and bent... the formed metal isn't...

 

the curved line is less likely to transmit though but the right angle can allow jumping of the ship so to speak...

 

this all takes me back to high school. thoroughly enjoyed this if I am remembering things the way I should...


Edited by _The Doctor__, Sun Sep 23, 2018 7:58 PM.


#133 Osgeld OFFLINE  

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Posted Sun Sep 23, 2018 8:20 PM

um finish line needs exacto knives and repair mask? runs and hides.

 

 

well it was a prototype pile of boards, most of the expense was reordering 50x 380mm by 110mm on a 3 day turn 

 

dem early day's, I found out and I almost threw up, boss told me "least its not a 80,000$ mistake" 

 

anyway back on topic, didnt mean to derail there 


Edited by Osgeld, Sun Sep 23, 2018 8:20 PM.


#134 Spaced Cowboy OFFLINE  

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Posted Sun Sep 23, 2018 9:00 PM

The majority of the traces are in fact 45-degree. Those that aren't are often inner layer and generated by the autorouter. I've sent off a support request about how to avoid them, but I suspect it's more repetitions of the 'recorner' command above.

I'm reasonably certain, though, that to an electron, a 4-mil trace is approximately ginormous, so the corner of the trace being sharp oughtn't matter at that scale. I'm paying for the high-res solder masking (0.1mm), so I ought to get decent etching. I guess we'll see, depending on if there's things I can do to remove them anyway.

#135 Osgeld OFFLINE  

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Posted Sun Sep 23, 2018 9:09 PM

autorouter, bless your heart

 

anyway solder masking has nothing to do with the copper etching, its the same process one might go though at home, you have bare FR4 which is laminated with copper, masked with your copper layers, etched chemically then solder mask is applied on top to keep the molten solder from moving around (too much) 

 

stuff happens in the etch process and that inside corner of a (square) 90 is going to be the very last thing that's going to be eaten away and it may just be a blemish, it may short vcc to ground, it may screw up one bit on a buss that drives you friggin nuts 

 

or it may never happen .... something may happen and good luck or nothing may happen though the entire life of the PCB 

 

I am not saying rip up your entire board and start over, just pointing out that the deck is tilting a card or 2 away from your favor :)


Edited by Osgeld, Sun Sep 23, 2018 9:12 PM.


#136 Spaced Cowboy OFFLINE  

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Posted Sun Sep 23, 2018 9:23 PM

autorouter, bless your heart


There's no way I'm doing that board by hand. Quoting from above: generally I route "important" signals by hand - things like power planes, power entry, differential pairs, clocks and busses and then let the autorouter take over and do "the rest". I'm aware that some consider that heresy [grin]

 

anyway solder masking has nothing to do with the copper etching, its the same process one might go though at home, you have bare FR4 which is laminated with copper, masked with your copper layers, etched chemically then solder mask is applied on top to keep the molten solder from moving around (too much) 
 
stuff happens in the etch process and that inside corner of a (square) 90 is going to be the very last thing that's going to be eaten away and it may just be a blemish, it may short vcc to ground, it may screw up one bit on a buss that drives you friggin nuts 
 
or it may never happen .... something may happen and good luck or nothing may happen though the entire life of the PCB 
 
I am not saying rip up your entire board and start over, just pointing out that the deck is tilting a card or 2 away from your favor :)


Fairy nuff - as I said I've asked how to mitigate it. The vast majority of the autorouter routes are in fact cornered at 45 degrees. I'm kind of wondering why the ones that aren't, aren't.



#137 Osgeld OFFLINE  

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Posted Sun Sep 23, 2018 9:29 PM

dunno, autorouters are dumb

 

at work we use Altium Designer, a stupid seat for that probally cost as much as my turd of a car is worth. Last time I let it autoroute something it put a power rail off the freaking PCB

 

(edit then proceed to complain about it when it did its live DRC)

 

:?


Edited by Osgeld, Sun Sep 23, 2018 9:31 PM.


#138 Spaced Cowboy OFFLINE  

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Posted Sun Sep 23, 2018 9:38 PM

dunno, autorouters are dumb

 

at work we use Altium Designer, a stupid seat for that probally cost as much as my turd of a car is worth. Last time I let it autoroute something it put a power rail off the freaking PCB

 

:?

 

 

So far ... nothing like that has been the case [grin].

 

The autorouter gets to write a script that Eagle then runs. Once that's done I click on DRC to see if there's anything wrong. Traces that veer too close to the edge would definitely trigger warnings. 

 

The autorouter does in fact (currently) give me a board that doesn't pass DRC, but that's because I gave it a board which I'd partially routed, and specified specific trace widths to force characteristic differential pair impedance - and then the autorouter hadn't noticed that and ended up placing a via too close to that trace. So currently after I've run the router, there's a little patch-work to do.

 

What is cool, though is that the developer has been working back and forth with me for a little while now, trying to figure out where exactly the problem lies, there's three possibilities 

 

 - The script that Eagle runs to convert its board to DSN format

 - The autorouter logic itself

 - The script that is generated to make Eagle duplicate the autorouted result

 

It'll get there. And all the support is free :)






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