carlsson Posted March 12, 2018 Share Posted March 12, 2018 Some people consider the zeropage as 256 registers, not me though. Quote Link to comment Share on other sites More sharing options...
phoenixdownita Posted March 13, 2018 Share Posted March 13, 2018 Some people consider the zeropage as 256 registers, not me though. Why not? It is used in a very special way and almost all instructions handle it (not so for the full address mode instead). In a way I consider A,X,Y as special cases of very fast architectural registers that are also exposed directly to the programmer for even faster and more compact routines (the x64 for example has hundreds of architectural registers internally but it only exposes 16 64bit addressable ones). That is obviously only my opinion and you don't have to agree also page0 reminds me a little of the registers-in-ram of TMS9900 design. Quote Link to comment Share on other sites More sharing options...
rpiguy9907 Posted March 14, 2018 Author Share Posted March 14, 2018 Should have said feels like it, not looks like it. Title of the thread: 6502 not technically RISC, but sure looks like it sometimes Quote Link to comment Share on other sites More sharing options...
JamesD Posted March 14, 2018 Share Posted March 14, 2018 Whole lotta feelings going on here Quote Link to comment Share on other sites More sharing options...
+OLD CS1 Posted March 17, 2018 Share Posted March 17, 2018 Why not? It is used in a very special way and almost all instructions handle it (not so for the full address mode instead). In a way I consider A,X,Y as special cases of very fast architectural registers that are also exposed directly to the programmer for even faster and more compact routines (the x64 for example has hundreds of architectural registers internally but it only exposes 16 64bit addressable ones). That is obviously only my opinion and you don't have to agree also page0 reminds me a little of the registers-in-ram of TMS9900 design. Reminiscent perhaps, but not the same. In the 9900 you can load a value directly into memory designated as workspace, and you can also address that same memory directly. You can do some neat stuff that way but that workspace RAM is still accessed in a single instruction when addressed as a register. For example, if your workspace is >8300, loading a value into R0 (register 0) puts that value in >8300, LI R1 into >8302, etc. Conversely you can pre-stage a register workspace in RAM at some other location then change the workspace to that location. For example, set up 16 words at >A300 then set the workspace to >A300 giving an instant change of all registers. Zero-page RAM takes multiple instructions, albeit short 2-byte instructions versus 3-bytes for non-zero-page. If you want to put a value into, say $0E, you have to LoaD the value into A, X, or Y, then STore that register into $0E. From my limited perspective that does not a register make though I do find it an advantage in its own way. For that matter being able to manipulate RAM in the second page ($01xx area) via the stack pointer can be quite handy, as well. Quote Link to comment Share on other sites More sharing options...
phoenixdownita Posted March 17, 2018 Share Posted March 17, 2018 Dunno even Wikipedia agrees on considering page0 for the 6502 as an "extended pool of extra registers". https://en.wikipedia.org/wiki/Zero_page Everyone knows that Wikipedia can't be wrong!!!! Quote Link to comment Share on other sites More sharing options...
+OLD CS1 Posted March 17, 2018 Share Posted March 17, 2018 Dunno even Wikipedia agrees on considering page0 for the 6502 as an "extended pool of extra registers". https://en.wikipedia.org/wiki/Zero_page Everyone knows that Wikipedia can't be wrong!!!! You just shivered me timbers. Quote Link to comment Share on other sites More sharing options...
JamesD Posted March 17, 2018 Share Posted March 17, 2018 Why not? It is used in a very special way and almost all instructions handle it (not so for the full address mode instead). In a way I consider A,X,Y as special cases of very fast architectural registers that are also exposed directly to the programmer for even faster and more compact routines (the x64 for example has hundreds of architectural registers internally but it only exposes 16 64bit addressable ones). That is obviously only my opinion and you don't have to agree also page0 reminds me a little of the registers-in-ram of TMS9900 design. Page 0 isn't used in a very special way, it's used exactly like extended addressing but the high byte is assumed to be 0. Nothing more. Dunno even Wikipedia agrees on considering page0 for the 6502 as an "extended pool of extra registers". https://en.wikipedia.org/wiki/Zero_page Everyone knows that Wikipedia can't be wrong!!!! Ah Wiki... edited by anyone that wants to. https://en.wikipedia.org/wiki/Addressing_mode#Simple_addressing_modes_for_code Quote Link to comment Share on other sites More sharing options...
ClausB Posted March 17, 2018 Share Posted March 17, 2018 Um, yes, something more. Page zero locations are used in indirect addressing modes. 2 Quote Link to comment Share on other sites More sharing options...
phoenixdownita Posted March 18, 2018 Share Posted March 18, 2018 Page 0 isn't used in a very special way, it's used exactly like extended addressing but the high byte is assumed to be 0. Nothing more. Ah Wiki... edited by anyone that wants to. https://en.wikipedia.org/wiki/Addressing_mode#Simple_addressing_modes_for_code Not sure your link meant to be sarcastic but on the same page a few paragraphs below: https://en.wikipedia.org/wiki/Addressing_mode#Zero_page "As a result, the zero page was used similarly to a register file." It seems that section it's been there unchallenged since 2006 .... one would think that if many people would take objection to that statement by now it would have been redacted/softened. Anyhow we are digressing, as already stated there was no RISC defined per se in 1975, the rest discussed is largely a matter of opinion. In specific my opinion is that page0 does resemble a register file (it is not a full fledged register file), your opinion seems different.... neither of us wins anything attempting to convince the other of his own blatantly obviously superior point of view .... just saying. Quote Link to comment Share on other sites More sharing options...
JamesD Posted March 18, 2018 Share Posted March 18, 2018 It's impossible to "win" when someone bases their opinion on how they feel 1 Quote Link to comment Share on other sites More sharing options...
+OLD CS1 Posted March 18, 2018 Share Posted March 18, 2018 Speaking of RISC, in my computer organization classes we programmed in MIPS. Not directly, we used SPIM to emulate a MIPS. IIRC one of the things MIPS does which is rather RISC-ey is eschews variable sized instructions. No one, two, or three byte instructions, they are all 32-bit instructions including any arguments. In the 6502 instructions are all single-byte but arguments can be one or two bytes. LDA #$08 is two bytes, STA $DD01 is three bytes, JMP ($0008),Y is three bytes, BNE/BEQ are two bytes, TAX, RTS, ROL are one byte, and so on. In one class project we had to write a MIPS program which did some tasks without stalling the pipeline. If you stalled the pipeline at all you failed the assignment. I loved that class, even installed SPIM on my Solaris box to play with. 1 Quote Link to comment Share on other sites More sharing options...
phoenixdownita Posted March 19, 2018 Share Posted March 19, 2018 Well I guess when I am coding on an ARM using Thumb2 instructions (or T32 if you prefer) which mix 16bits and 32bits long instructions I am mysteriously stepping out of the ARM v6/v7 chip being considered RISC and into quantum foam territory in which now it is something totally different. Quote Link to comment Share on other sites More sharing options...
zzip Posted March 19, 2018 Share Posted March 19, 2018 Everyone knows that Wikipedia can't be wrong!!!! It doesn't say that anymore.. wink wink Quote Link to comment Share on other sites More sharing options...
phoenixdownita Posted March 19, 2018 Share Posted March 19, 2018 It doesn't say that anymore.. wink wink It doesn't? Quote Link to comment Share on other sites More sharing options...
JamesD Posted March 19, 2018 Share Posted March 19, 2018 Editing the Wiki to support your BS argument is BS Quote Link to comment Share on other sites More sharing options...
carlsson Posted March 19, 2018 Share Posted March 19, 2018 (edited) By the way, perhaps it is the RISC paradigm that isn't technically 6502 compatible but sure looks like it sometimes? Edited March 19, 2018 by carlsson 1 Quote Link to comment Share on other sites More sharing options...
phoenixdownita Posted March 19, 2018 Share Posted March 19, 2018 I never touched a wiki page, so not sure who James is mad at. Quote Link to comment Share on other sites More sharing options...
+OLD CS1 Posted March 19, 2018 Share Posted March 19, 2018 I think as a Wiki Editor you can "subscribe" to a page to get notification when it gets updated. It is possible someone is watching the page for that particular information and changing it back. Such activity has caused pages to be locked before, usually I have seen it involving a societal or political hot-topic or person. But then I tend not to cruise Wikipedia. Quote Link to comment Share on other sites More sharing options...
phoenixdownita Posted March 19, 2018 Share Posted March 19, 2018 Would't those edit be in the history anyway? When I looked at the history I didn't see any edit/revert ... given I didn't put that info there to begin with and I am not sure if zzip meant to say he edited it or if JamesD did it or someone else, whatever it is I'd say let it be. In the end I liked this article: http://ethw.org/Why_Instruction_Sets_No_Longer_Matter it wasn't really CISC vs RISC but fast integrated caches and in general memory hierarchy that mattered and still does and can explain why the x64 is still so competitive with its CISC ISA. 1 Quote Link to comment Share on other sites More sharing options...
thetick1 Posted March 22, 2018 Share Posted March 22, 2018 Would't those edit be in the history anyway? When I looked at the history I didn't see any edit/revert ... given I didn't put that info there to begin with and I am not sure if zzip meant to say he edited it or if JamesD did it or someone else, whatever it is I'd say let it be. In the end I liked this article: http://ethw.org/Why_Instruction_Sets_No_Longer_Matter it wasn't really CISC vs RISC but fast integrated caches and in general memory hierarchy that mattered and still does and can explain why the x64 is still so competitive with its CISC ISA. Excellent link! Caches (L1,L2,L3,L4) and their coherency schemes matter most when it comes to performance. Quote Link to comment Share on other sites More sharing options...
JamesD Posted March 22, 2018 Share Posted March 22, 2018 I've never edited a Wiki article and have no desire to do so. The person that did, clearly based the entry on their opinion.Good article, but the article overlooks code density. It's about presenting the code to the ALU as fast as possible with the least amount of stalls to the pipeline. A more CISC like instruction set uses less RAM and reduces the amount of memory bandwidth required to keep the cache loaded. Branch prediction is essential to keep the cache loaded and prevent stalls.CISC vs RISC is largely irrelevant now, but a more efficient CISC or regular RISC design requires a smaller die, is much cheaper, and more power efficient.It depends on what you want to do. What that has to do with the 6502 I don't know. Quote Link to comment Share on other sites More sharing options...
thetick1 Posted March 22, 2018 Share Posted March 22, 2018 What that has to do with the 6502 I don't know. Basically nothing as the 6502 is not really a processor by modern standards but a microcontroller. Quote Link to comment Share on other sites More sharing options...
zzip Posted March 22, 2018 Share Posted March 22, 2018 It doesn't? It was just an "I edited Wikipedia to support my POV" joke. I didn't actually edit the article though. Quote Link to comment Share on other sites More sharing options...
rpiguy9907 Posted April 5, 2018 Author Share Posted April 5, 2018 The inventor of MIPS, Hennessy did a very mathematical analysis of RISC vs. CISC. On average the CISC processors of the day took 6 times as long as a RISC processor to fully fetch, execute, and resolve an instruction. The code density of the available CISC processors were twice as efficient (required half the number of instructions) as RISC. This still have the RISC processors a 3x inherent advantage over CISC processors. This is true of mid-80s CISC processors, but as their busses widened you see that gap narrow already. Suddenly instead of taking 6 times as long, they only take 4 times and long or 3 times as long, and so the advantage starts to thin. Quote Link to comment Share on other sites More sharing options...
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