Last session we learned that the playfield registers PF0 and PF2 are reversed. Specifically, the order of pixels in the playfield registers (one bit per pixel, remember!) is backward, compared to the order for the first playfield register we encountered - PF1. This backward ordering is rather confusing, but that's just the way it is. Have a close look at the diagram presented in the last session and try and understand exactly the "playfield register/bit" to "pixel position on the scanline" correspondence.
There's one new playfield-related capability of the '2600 which I'd like to introduce now - playfield mirroring. I've already introduced this to you when I stated that the right hand side of the playfield was a copy of the left hand side (that is, the left 20 pixels come from the 20 playfield bits held in the TIA registers PF0, PF1 and PF2 - and the right 20 bits are a copy of the same bits). That copy can be displayed "normally" - or "mirrored". When mirrored, the bits are literally a mirrored copy of the left side of the playfield.
We're already familiar with two 'types' of TIA register. There's the strobe-type, where a write of any value to the register causes something to happen, independent of the value written (an example is WSYNC, which halts the 6502 until the TIA starts the next scanline). A second type is the normal register to which we write a byte, and the TIA uses that byte for some internal purpose (examples of these are the playfield registers PF0, PF1 and PF2). PF0 was a special-case of this type, where - though we wrote a byte - only four of the bits were actually used by the TIA. The remaining bits were discarded/ignored (have a look at the PF0 register in the diagram in the last session - the X for each bit position in bits D0-D3 indicates those bits are not used).
The third type of register (they're not really 'types' - but I want you to understand the difference between the way we're writing data to the TIA) is where we are interested in just the state of a single BIT in a register. Time to introduce a new TIA register, called CTRLPF. It's located at address 10 ($A)
CTRLPF This address is uded to write into the playfield control register (a logic 1 causes action as described below) D0 = REF (reflect playfield) D1 = SCORE (left half of playfield gets color of player 0, right half gets color of player 1) D2 = PFP (playfield gets priority over players so they can move behind the playfield) D4 & D5 = BALL SIZE D5 D4 Width 0 0 1 clock 0 1 2 clocks 1 0 4 clocks 1 1 8 clocks
Wow! This register has a lot of different stuff associated with it! Most of it is related to playfield display (bits D0, D1, D2) but bits D4 and D5 control the "BALL SIZE" - we'll worry about those bits later
Bit D0 controls the reflection (mirroring) of our playfield. If this bit is 0, then we have a "normal" non-mirrored playfield, and that's what we've been seeing so far in our demos. If we set this bit to 1, then the '2600 will display a reflected playfield (that is, the right-side of the playfield is a mirror-image of the left-side, instead of a copy). Note that only a single bit is used to control this feature - if we wrote a byte with this bit set (ie: %00000001) to CTRLPF we would also be setting those other bits to 0 - and we should be very sure this is what we want. In fact, it's often NOT what we want, so when we are writing to registers such as this (which contain many bits controlling different parts of the TIA hardware/display), we should be very careful to keep all the bits exactly as we need them. Sometimes this is done with a "shadow" register - a RAM copy of our current register state, and by first setting or clearing the appropriate bit in the shadow register, and THEN writing the shadow register to the TIA register. This is necessary because many/most of the TIA registers are only writeable - that is, you cannot successfully read their contents and expect to get the value last written.
Let's have a quick look at those other bits in this register, related to playfield...
D1 = SCORE. This is interesting. Setting this bit causes the playfield to have two colours instead of one. The left side of the playfield will be displayed using the colour of sprite 0 (register COLUP0), and the right side of the playfield will be displayed using the colour of sprite 1 (register COLUP1). We won't play with this for now - but keep in mind that it is possible. Remember, this machine was designed for PONG-style games, so this sort of effect makes sense in that context.
D2 = PFP. Playfield priority. You may have the playfield appear in front of, or behind, sprites. If you set this bit, then the playfield will be displayed in front, and all sprites will appear to go behind the playfield pixels. If this bit is not set, then all sprites appear to go in front of the playfield pixels.
That's a very quick rundown of this register. We know now that it controls the playfield mirroring (=reflection), the playfield colour control for left/right halves, the playfield priority (if sprites go in front of or behind the playfield), and finally it does something with the "BALL SIZE" which we're not worring about yet.
I've indicated that it's useful to have a "shadow" copy of the register in RAM, so that we can easily keep track of the state of this sort of register. In practise, this is rarely done - as we generally just set the reflection on or off, the score colouring on or off, the priority on or off, and the ball size as appropriate... and then forget it. But if, for example, you were doing a game where you were changing the priority on the fly (so your sprites went behind SOME bits background, but not other bits) then you'd need to know what those other values should be.
In any case, the point of this is to introduce you slowly to more TIA capabilities, and at the same time build your proficiency with 6502 programming. Here's how we set and clear bits with 6502.
CTRLPF_shadow = $82 ; a RAM location for our shadow register lda #%00000000 sta CTRLPF_shadow ; init our shadow register as required ; lots of code here lda CTRLPF_shadow sta CTRLPF ; copy shadow register to TIA register
The above code snippet shows the general form of shadow register usage. The shadow register is initialised - and at some point later in the code, we copy it to the TIA register. Now for the fun bit - setting and clearing individual bits in the shadow register...
; how to set a single bit in a byte lda CTRLPF_shadow ; load the shadow register from RAM ora #%00000001 ; SET bit 0 (D0 = 1) sta CTRLPF_shadow ; save new register value back to RAM ; how to clear a single bit in a byte lda CTRLPF_shadow and #%11111110 ; keep all bits BUT the one we want to clear sta CTRLPF_shadow
OK, that's not too difficult to understand. The two new 6502 instructions we have just used are "ORA", which does a logical-OR (that is, combines the accumulator with the immediate value bit-by-bit using a OR operation) - and the "AND", which does a logical-AND (again, combines the accumulator with the immediate value bit-by-bit using an AND operation). Now this is getting into pretty basic binary math - and you should read up on this stuff if you don't already know - but here's some truth tables for you...
OR operation BIT | 0 1 -----+------------ 0 | 0 1 | 1 | 1 1 AND operation BIT | 0 1 -----+------------ 0 | 0 0 | 1 | 0 1
Basically the above two tables give you the result FOR A SINGLE BIT POSITION, where you either OR or AND together two bits. For example, if I "OR" together 1 and 0, the resultant value (bit) is 1. Likewise, if I "AND" together a 1 and 0, I get a 0. This logical operation is performed on each bit of the accumulator, with the corresponding bit of the immediate value as part of the instruction. So "ora #%00000001" will actually leave the accumulator with the lowest bit SET. No matter what. Likewise, "and #%11111110" will leave the accumulator with the lowest bit CLEAR. No matter what. And in the other bits, their value will remain unchanged. You should try some values and check this out, because understanding this binary logical operation on bits is pretty fundamental to '2600 programming.
In the initialisation section of your current kernel, add the following lines...
lda #%00000001 sta CTRLPF
That's our playfield reflection in operation - if you're running any sort of playfield code, you will see that the right-side is now a mirror-image of the left-side. Now have a think about the exercise I offered in session 14...
Andrew Davie said:
Note: this would form a "box" border around the entire playfield.
It should be apparent, now, that in this sort of situation we really only need to worry about the left side of the playfield! If we let the '2600 reflect the right side, we will get a symmetrical copy of the left, and we'll have our box if only we do the left-side borders. This is a huge advantage to the programmer, because we suddently don't have to write new PF0, PF1, PF2 values each scanline. Remember (and I'll drum this into you until the very last session!) we only have 76 cycles per scanline - the less we have to do on any line, the better. At the very least, rewriting PF0, PF1 and PF2 twice per scanline would cost 30 cycles IF you were being clever. That's almost half the available time JUST to draw background - and there's still colours, sprites, balls and missiles to worry about! However, if you just use a reflected playfield, then we are only looking at single writes to PF0, PF1, PF2, cutting our playfield update to only 15 cycles per line (eg: lda #value / sta PF0 / lda #value2 / sta PF1 / lda #value3 / sta PF2).
Just an aside, here - some people have been posting code IN UPPERCASE. It is quite acceptable to use upper or lowercase for the mnemonics of your 6502 code. I prefer lowercase, as I find it easier to read and LESS LIKE SHOUTING! But its totally up to you - you will typically (but not always) find my code is lowercase, and you may feel free to adopt a style that suits you. I make my constants UPPERCASE, my variables typically a mixture, and my mnemonics lower-case. Your mileage may vary.
So, let's get down to it - here's a solution for exercise 5, of session 14...
; '2600 for Newbies ; Session 15 - Playfield Continued ; This kernel draws a simple box around the screen border ; Introduces playfield reflection processor 6502 include "vcs.h" include "macro.h" ;------------------------------------------------------------------------------ SEG ORG $F000 Reset ; Clear RAM and all TIA registers ldx #0 lda #0 Clear sta 0,x inx bne Clear ;------------------------------------------------ ; Once-only initialisation... lda #$45 sta COLUPF ; set the playfield colour lda #%00000001 sta CTRLPF ; reflect playfield ;------------------------------------------------ StartOfFrame ; Start of new frame ; Start of vertical blank processing lda #0 sta VBLANK lda #2 sta VSYNC sta WSYNC sta WSYNC sta WSYNC ; 3 scanlines of VSYNC signal lda #0 sta VSYNC ;------------------------------------------------ ; 37 scanlines of vertical blank... ldx #0 VerticalBlank sta WSYNC inx cpx #37 bne VerticalBlank ;------------------------------------------------ ; Do 192 scanlines of colour-changing (our picture) ldx #0 ; this counts our scanline number lda #%11111111 sta PF0 sta PF1 sta PF2 ; We won't bother rewriting PF0-PF2 every scanline of the top 8 lines - they never change! Top8Lines sta WSYNC inx cpx #8 ; are we at line 8? bne Top8Lines ; No, so do another ; Now we want 176 lines of "wall" ; Note: 176 (middle) + 8 (top) + 8 (bottom) = 192 lines lda #%00010000 ; PF0 is mirrored <--- direction, low 4 bits ignored sta PF0 lda #0 sta PF1 sta PF2 ; again, we don't bother writing PF0-PF2 every scanline - they never change! MiddleLines sta WSYNC inx cpx #184 bne MiddleLines ; Finally, our bottom 8 scanlines - the same as the top 8 ; AGAIN, we aren't going to bother writing PF0-PF2 mid scanline! lda #%11111111 sta PF0 sta PF1 sta PF2 Bottom8Lines sta WSYNC inx cpx #192 bne Bottom8Lines ;------------------------------------------------ lda #%01000010 sta VBLANK ; end of screen - enter blanking ; 30 scanlines of overscan... ldx #0 Overscan sta WSYNC inx cpx #30 bne Overscan jmp StartOfFrame ;------------------------------------------------------------------------------ ORG $FFFA InterruptVectors .word Reset ; NMI .word Reset ; RESET .word Reset ; IRQ END
This kernel is interesting in that it achieves the box effect by writing the playfield registers BEFORE the scanline loops to do the appropriate section. It uses the knowledge that the TIA has an internal state and will keep displaying whatever it already has in the plafyield registers. So, in fact, the actual cost (in cycles) of drawing the "box" playfield on each scanline is 0 cycles - ie; it's free. We just had that short initial load before each section (taking a few cycles out of the very first scanline of each section). This is how you need to think about '2600 programming - how to remove cycles from your scanlines - and do the absolute minimal necessary.
That will do for today's session. We've had an introduction to controlling individual TIA register bits, and seen how to achieve a reflected playfield at next to no cost. We've had a brief introduction to the CTRLPF register, and seen how it has a myriad (well, more than 3) uses. Although some of the previous sessions have asked you to think about tricky subjects like horizontal scrolling, and asymmetrical playfields - now is not the time to actually discuss these tricky areas. Those who have been posting their sample solutions are on the right track. We'll get to those areas in future sessions - so until next time (when we'll develop our playfield skills a bit more)... ciao!
1. Introduce a RAM shadow of the CTRLPF register, and modify it differently in each section of the kernal. For example turn reflection on and off partway through the midsection of the box, and see what happens.
2. Have a play with the SCORE bit in the CTRLPF register, and in conjunction with that the COLUP0 and COLUP1 colour registers. Note how this SCORE bit changes where the colour for the playfield comes from.