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Minimal Demo

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#26 iesposta OFFLINE  


    River Patroller

  • 3,880 posts
  • Retro-gaming w/my VCS
  • Location:Pennsylvania

Posted Sat Oct 6, 2018 6:17 PM

So, my final result of 32 byte demo coding is now available here: https://xayax.net/hard2632/

More discussion after the demo party! :)

That is so cool! And on a dip-switch re-configurable 32b circuit board!


Good luck at the demo party!


Now how much sound can be made if you don't have to worry about keeping a display?

Some of those simple math equations can create very intricate "songs".

#27 JeremiahK OFFLINE  


    Chopper Commander

  • 221 posts
  • Location:Indiana, USA

Posted Sat Oct 6, 2018 9:31 PM

Nice!  Now I need one of those dip-switch boards...


I haven't looked at your code yet, but I noticed the angled border lines are spaced by 9 scanlines, which makes me suspect you are ROLing the value in PF1.


Edit: That's some tight code!  How do the NMI/BRK/RESET vectors work?

Edited by JeremiahK, Sat Oct 6, 2018 9:55 PM.

#28 SvOlli OFFLINE  


    Chopper Commander

  • Topic Starter
  • 214 posts
  • Location:Hannover, Germany

Posted Sun Oct 7, 2018 12:25 PM

I tried the following idea: bne is $D0, if the I find a loop that's 16 bytes back or less, this encodes as $D0, $Fx, or as a word $FxD0.


So I utilized the mirroring and rotated the code to have a BNE at the reset vector. With the second BNE the trick worked: $F9D0 now is inside the reset routine. All I needed to do there was to reorder the code there, so the BNE there will always branch after reset.


This is something that won't work without the help of an assembler and Stella. I want to code a slightly simpler demo just using the first table from http://www.oxyron.de.../opcodes02.html and assemble the code to hex/binary/dipswitches not using any "computer-based" tooling.

#29 Omegamatrix OFFLINE  



  • 6,222 posts
  • Location:Canada

Posted Sun Oct 7, 2018 1:20 PM

The board is a cool idea. :) I thought this thread was dead because no one was submitting demos, but seeing the board inspired me some more.


So here are my final two demos.




Attached File  NewDemos.zip   1.29KB   66 downloads

Edited by Omegamatrix, Sun Oct 7, 2018 1:28 PM.

#30 Omegamatrix OFFLINE  



  • 6,222 posts
  • Location:Canada

Posted Mon Oct 8, 2018 12:39 PM

I made a new demo, Animatrix 2. I like it a little better than the original Animatrix.

; 32 byte demo, Animatrix 2
; by Omegamatrix

; last update Oct 08, 2018

    processor 6502
    include vcs.h

    ORG $F800
    .byte $FF

    ORG $FFE0


;SP=$FD at startup

    bne    .loopClear

;RIOT ram $80-$F6 clear, TIA clear, SP=$FF, A=0, X=0, carry is clear

    lda    #$38         ; does two lines (non-Vsync), and then the regular 3 lines of VSYNC
    sta    GRP0
    sta    WSYNC
    sta    VSYNC
    bne    .loopVSYNC

    sty    HMP0

    sta    WSYNC
    sta    HMOVE
    sty    COLUP0
    bne    .loopKernel
                          ; X=0
    ORG $FFFC             ; CPX #$FF
    .word Start
    bne   .doVSYNC        ; always branch

Attached File  Animatrix 2.bin   2KB   70 downloads

Edited by Omegamatrix, Mon Oct 8, 2018 3:44 PM.

#31 Tjoppen OFFLINE  


    Chopper Commander

  • 221 posts

Posted Mon Oct 8, 2018 1:27 PM

Did y'all open an issue?


attachicon.gifScreen Shot 2018-09-11 at 10.15.44 AM.png


And was are dumb misspelt to make it a 666 byte source file?


Nope, didn't notice that. Just frustrated with Stella and Harmony

#32 Wintermute OFFLINE  


    Combat Commando

  • 1 posts

Posted Tue Jan 1, 2019 3:45 PM

I guess I'm a bit late to the party, but here goes -- I finally got around to doing this challenge at 35C3 last week.
My approach is a little unorthodox in that the hardware initialisation happens in a single byte at the bottom of the screen loop. This comes at the cost of an up to approximately four seconds long "boot" period during which the VCS may (but rarely does, at least in randomly initialized Stella) show garbage in addition to the effect because only one zero byte is pushed per screen. I consider this acceptable given the space constraints, but YMMV.
SvOlli calls this "precomputation," so I guess there's a VCS demo that does that now.
Details are in the source code comments. It's possible more can be squeezed from this that I don't see; I'm afraid I'm nowhere near as experienced with the VCS as some (most? all?) people here.  ;-)

   processor 6502

   list off
   include vcs.h
   list on

; reset vector at OFFSET - 4

   seg code
   org $f3c1

; upon reset expected: SP = $fd
; also expected: mirroring every 32 bytes

; Look, ma, no init routine! :P
; Except not really, of course. I'm doing HW init in one pha at the bottom of the screen loop.
; This is a trade-off: I get only one zero-byte per screen in exchange for four extra bytes
; of machine code that I (desperately) need, especially since I also need to cld in order to
; be able to use adc #1 (which takes one more byte than inx, iny).
; Depending on the initial state, the demo may show nonsense during the first ~4 seconds. This
; can be random garbage in PF0, a strange background color, a sprite or anything else. It's
; surprisingly rare at least in Stella with random initial state, though.

   lda   #$3b              ;  0 -- Bit of luck: this pattern looks nice in PF1,2 and works well
   sta   PF1               ;  2 -- in CTRLPF: reflect | score | unimportant stuff. Weirdly, even
   sta   PF2               ;  4 -- the usually frustrating mirroring of PF1 that makes horizontal
   sta   CTRLPF            ;  6 -- scrolling such a pain works to my advantage.
   	 		   ;       Feel free to try other patterns. It's only important that
			   ;       SCORE is set, PFP is not set, and possibly that three consecutive
			   ;       bits are set so that the sync block works, although I'm unsure
			   ;       of the exact semantics there. It works in Stella with #$0b, which
			   ;       kinda surprised me.
   lsr                     ;  8 -- this part inspired by (lifted from) SvOlli
   sta   WSYNC             ;  9
   sta   VSYNC             ; 11
   bne   sync              ; 13 -- Reset vector no longer here, though; this points between
                           ;       instructions now. See below.

   tsx                     ; 15 -- S doubles as counter for the right topmost color.
   dex                     ; 16 -- Walk through the rainbow, one color every line.
   dey                     ; 17 -- Variation: iny instead of dey here. I like dey better. iny
                           ;       feels like inconsistent shadows to me.
   sta   WSYNC             ; 18
   sty   COLUP0            ; 20 -- set new colors
   stx   COLUP1            ; 22
   cld                     ; 24 -- Having cld close to the adc instruction keeps the invalid region
                           ;       for the reset vector small. Doesn't matter that it's execd often.
   adc   #1                ; 25 -- A from 0 to 0, carry set at outset => 255 scanlines per screen.
                           ;       This means that Y increases by 1 each screen (dey 255 times)
   bne   line              ; 27 -- doubles as reset vector (f3d0), happens to point at 15: tsx.
                           ;       Any instruction except the adc would be fine, though. The reason
			   ;       adc is not fine is that the CPU could be in BCD mode after reset.
			   ;       On that note, whoever invented BCD ought to be clipped round the ear.
   pha                     ; 29 -- A is 0 here, so this will eventually init hw.
   beq   screen            ; 30

Attached Files

Edited by Wintermute, Tue Jan 1, 2019 3:53 PM.

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