Jump to content

Photo

M1 delay

timing cycles M1

2 replies to this topic

#1 ThomH OFFLINE  

ThomH

    Chopper Commander

  • 166 posts

Posted Fri Jan 11, 2019 11:54 AM

Looking at this schematic I see a 74LS74A which appears to be set up to trigger a cycle of WAIT upon every M1.

 

That's not too uncommon for Z80 machines because it extends the opcode fetch read from 2 cycles to 3, moving it into line with most other accesses. It's even offered as a sample external circuit in at least one of the Z80 data sheets.

 

Yet I've never heard about that in ColecoVision world. It would if I'm reading things correctly give operations the same cost as on the MSX. So e.g. NOP would take 5 cycles, not 4.

 

Since I trust my schematic reading maybe only 70%, having no formal grounding in electronics, can anybody confirm or deny that the ColecoVision inserts an extra cycle into every M1 machine cycle?



#2 ChildOfCv ONLINE  

ChildOfCv

    Star Raider

  • 81 posts

Posted Fri Jan 11, 2019 12:25 PM

Yep, that wait cycle is there.

 

It also has a wait state when sending data to the sound chip.



#3 ChildOfCv ONLINE  

ChildOfCv

    Star Raider

  • 81 posts

Posted Fri Jan 11, 2019 12:48 PM

Also, if you're taking a more serious look at the CV schematics, I'll shill for my own schematics, which I've also gone through the trouble of verifying.  More consistent labeling, and all connections represented, and also a PCB diagram to help locate the components.  Contains PDF and Kicad formats.  Also shows schematic for the regular controller, Super Action Controller, and Roller Controller.

 

Comments welcome.

 

http://atariage.com/...ion-schematics/







Also tagged with one or more of these keywords: timing, cycles, M1

0 user(s) are browsing this forum

0 members, 0 guests, 0 anonymous users