NEW MIO production run.

[ataridano]

I am currently working with the board, to decide how Im going to wire the RAM logic. (notice empty sockets in the RAM area).. This is very timing dependant, and is going to require some additional testing..

 

Stay tuned for more updates....

 

Is it safe to assume that the idea is to add some more address decoding to allow the use of a >1M SIMM? Guess I'll have to watch for those updates

[MEtalGuy66]

Is it safe to assume that the idea is to add some more address decoding to allow the use of a >1M SIMM? Guess I'll have to watch for those updates

 

 

Well, since the MIO is originally one-meg, all of the necessary signals are present to adress 1 meg. What I am currently debating, as far as the RAM goes, is the exact bus-timing for A9 (the additional bit of adressing that allows use of one contiguous 1meg bank, rather than 4 separate 256k banks selected by 4 sets of CAS and RAS strobes). For one thing, A9 needs to be brought to state somewhat close to the existing A0-A8 within the bus cycle, in both cases of CAS and RAS.. Also, All 10 bits of adress must be in place, and stable, at the time that CAS or RAS is asserted. So.. What Im doing right now, is experimenting with several different logic configurations, in order to detemine which produces the best results.

[Mathy]

Howdy Ken

 

This might be a stupid suggestion, as I don't know much about the stuff, but why not use the methode that was used when upgrading the XL or XE. They somehow used a 74LS158 to create that extra refresh bit.

 

BTW everything over 256 bits has "autorefresh". You just tell the RAM to refresh itself.

 

(All of a sudden, I get the impression that we're talking about two different things. Do you have the schematics to the MIO in electronic form. If I kow what I am talking about, I make more sense.)

 

Greetings

 

Mathy

[+warerat]

Is it safe to assume that the idea is to add some more address decoding to allow the use of a >1M SIMM? Guess I'll have to watch for those updates

 

 

Well, since the MIO is originally one-meg, all of the necessary signals are present to adress 1 meg. What I am currently debating, as far as the RAM goes, is the exact bus-timing for A9 (the additional bit of adressing that allows use of one contiguous 1meg bank, rather than 4 separate 256k banks selected by 4 sets of CAS and RAS strobes). For one thing, A9 needs to be brought to state somewhat close to the existing A0-A8 within the bus cycle, in both cases of CAS and RAS.. Also, All 10 bits of adress must be in place, and stable, at the time that CAS or RAS is asserted. So.. What Im doing right now, is experimenting with several different logic configurations, in order to detemine which produces the best results.

 

Here's an idea. Your mileage may vary.

 

As you have a unified CAS/RAS on your 1MB SIMM, get your CAS from U23 pin 7, and get your RAS from U21, pin 6. That completely elimates the 'LS139 2-4 decoder at U22 for the four banks. From there you can mux pin 2 and pin 7 on U24 to get your A9.

Edited July 25, 2006 by warerat

[danwinslow]

I was gonna say that, but you beat me, dang it.

Edited July 27, 2006 by danwinslow

[MEtalGuy66]

 

Here's an idea. Your mileage may vary.

 

As you have a unified CAS/RAS on your 1MB SIMM, get your CAS from U23 pin 7, and get your RAS from U21, pin 6. That completely elimates the 'LS139 2-4 decoder at U22 for the four banks. From there you can mux pin 2 and pin 7 on U24 to get your A9.

 

Wow! I tried that... ANd I now have a 14 megabyte ramdisk configured with only a 1meg SIMM in the socket!

 

This is better than that disney movie where the aliens made the kid dream an electronic scematic of a circuit board he could build that produced oxygen out of nowhere..

 

Heheh. Just kidding... It did get it "seeing" the RAM though.. But the 14megs is obviously due to bad data in the configuration area. I think I still have some timing issues.

 

I did get the firmware to read 100% concrete.. Was a "defective" trace on the board on D1... All the boards have it too. Im gonna email a picture of it to the manufacturer, along with the layout file I submitted them for manufacturing, to prove I didnt cause it... And maybe I can get some kind of discount out of them on my next run of boards... Ive never seen them make a board before that wasnt 100% true to the cad file..

 

All this really means to us, for this prduction run, is "one more blue wire"...

[MEtalGuy66]

UPDATE: 07-29-06

 

SCSI is working...

 

256K ramdisk/printspooler is working..

 

Still working on the refresh circuit for 1meg SIMMS..

[Stephen J. Carden]

UPDATE: 07-29-06

 

SCSI is working...

 

256K ramdisk/printspooler is working..

 

Still working on the refresh circuit for 1meg SIMMS..

Ken, I wonder if anyone relizes how much time we have spent on the phone?

 

Here are the mux Boards.

 

Notice the chips, and dip switch.

 

Steve

[mio2repair]

Hello,

I wonder what the MUX boards are for?

Hope I don't sound dumb.

Some kind of cartrige stacking or adding a 6522?

ICD 1 meg MIO with case on Ebay or feebay etc.

Cy

[+Guitarman]

Taken from the CSS website

 

The Multiplexer

 

This device brings the power and flexibility of larger systems to your 8-bit. The Multiplexer is a collection of cartridge interface boards that allow up to 8 Ataris to read and write to the same drives (typically a hard disk), access the same printer(s), and talk to each other. It is the first practical networking system for the Atari 8-bit computer.

 

One "master" computer (any 8-bit) is equipped with the master Multiplexer interface. Then up to 8 "slave" computers hook up to this master, each having their own slave interface. The slave interface consists of a cartridge that plugs into the cartridge port. It has its own socket on the top so you can use whatever cartridges you desire with the system.

 

The "common" peripherals (things that are to be shared) are connected to the master. On each slave, all disk and printer I/O is routed through the master so no extra disk drives are needed. The master computer can be configured in any manner you wish. You may have certain peripherals local to the slave or routed to a different number on the master. Note that serial ports (R: RS232 interfaces) are not multiplexed. All slaves are independent and do not need to have the same program running on them.

[MEtalGuy66]

Progress report on MIO:

 

Well I feel like I need to report something..

 

We have the MIO adressing and refreshing every bit of a 1meg simm.

 

What we are doing now is evaluating signal timing, to try to get the maximum compatability with all

30-pin 1meg SIMM manufacturers..

 

 

I'd like to thank WARERAT for donating many hours of his time (and bringing over his logic analyzer).

 

Also, ALMOST RICE has let me borrow his stock 130xe and Spartados X cart for testing purposes.

[mio2repair]

Hello.

Note thaat there are a few odd 30 pin SIMs made for IBM PS/2 that had different parity pinout mostly.

Could be used if possible pin swap or parity ignored check pinout

lists for needed changes if any.

Anybody have SpartaDos X cart schematic?

Cy

[MEtalGuy66]

MIO progress report:

 

I have excellent news to report.

 

I have the new MIO board working with 1meg and 4meg 30pin SIMMS.

(4meg simms can be used, but it only uses the first 1024k. 8meg simms should work fine as well, but I dont have any to test)

I have tested at least 10 different brands of SIMMs, both parity and non parity..

 

I have run the burn-in test which REALLY "tortures" the ram by reading and writing multiple locations in all 4096 access "pages" extremely fast. I have run this test for 6 hours (over 100,000 complete test iterations)with 0 errors, and have also sector copied an entire 512k disk image of real-dos to the MIO ramdisk, turned off the atari for 1 hour, then powered the atari back up, and booted from the MIO ramdisk with no errors..

 

 

This is looking really good.

 

The only thing left now is the actual assembly and burn-in test of the actual production boards. This is going to take some time, but I will make sure that every last one of them is assembled to the highest possible standards and fully tested. I will be shipping these units as soon as they are built & tested.

 

I will build, test, and ship these in the same order, that the actual orders/payments were recieved. In other words, those who ordered/paid first will recieve their boards first. This is the only fair way I know to do it, since It will probably take me a month or more to assemble all of them.

[danwinslow]

I can send you a box full of old simms if you want. There's bound to be some 8 meggers in there.

 

 

*edit*

Oh, and I am sure it would be hard to bankswitch the extra 3 MB in and out, as you probably dont have lines for it, or whatever, but man that would be cool.

Edited August 8, 2006 by danwinslow

[+warerat]

I can send you a box full of old simms if you want. There's bound to be some 8 meggers in there.

 

 

*edit*

Oh, and I am sure it would be hard to bankswitch the extra 3 MB in and out, as you probably dont have lines for it, or whatever, but man that would be cool.

 

It's very possible, only two more ICs. Another latch for the additional two address bits and mux them together for A10. The firmware would just have to be modified to use 16384 pages instead of 4096 and add the code to address the additional latch.

[danwinslow]

Well, MG wanted to remain strictly comparable with this run I think. Although I would bet he could sell a modified version that would bankswitch larger simms. I would sure buy one. Even just a manual external switch to select banks 1,2,3 or 4 would be great...it'd be like having 4 complete setups to switch between at the flick of a button.

[MEtalGuy66]

Yes, this run is going to be 100% MIO compatable from a hardware standpoint. HOWEVER..

 

We are going to fix the firmware at some point, and correct the drive compatability issue..

 

And since we are planning to fix the firmware.. Here is something to think about..

 

The MIO accesses the RAMdisk in the following way..

 

There are 2 registers: BANK and PAGE.. BANK can have values of 00-0F (16 banks)... PAGE can have values of (00-FF) 256 pages.. each "page" of memory is 256bytes..

 

The combination of these two registers controls which 256byte "page" shows up in the atari's actual adress space.

 

What if we allowed BANK to have values from 00-FF (256 banks).... That would give us 16 megs of ramdisk without taking up any more of the atari's adress space, and also maintaining the 2-byte register format.

 

This should only require 2 more multiplexed adress lines to the SIMM.. There are already enough extra chip footprints on the existing board desgin to do this. The only downside is that 16meg 30pin SIMMS are rare as hell..

[ataridano]

Yes, this run is going to be 100% MIO compatable from a hardware standpoint. HOWEVER..

 

<snip>

 

What if we allowed BANK to have values from 00-FF (256 banks).... That would give us 16 megs of ramdisk without taking up any more of the atari's adress space, and also maintaining the 2-byte register format.

 

This should only require 2 more multiplexed adress lines to the SIMM.. There are already enough extra chip footprints on the existing board desgin to do this. The only downside is that 16meg 30pin SIMMS are rare as hell..

 

I realize that you're probably trying to use the current PCBs but what about using a 72 pin SIMM or multiple 30 pin SIMMS (I thought 4 meg SIMMS were rare as hell, I didn't think anything bigger existed). Could a daughter board be attached without a great deal of trouble?

[DamageX]

I have a few sets of 4MB SIMMs but I've never seen the rumored 8 or 16MB ones. I'd bet 1MB are the most common.

 

Ken, were you planning to improve the HDD support in the firmware also before sending the boards out?

[MEtalGuy66]

Yes, this run is going to be 100% MIO compatable from a hardware standpoint. HOWEVER..

 

<snip>

 

What if we allowed BANK to have values from 00-FF (256 banks).... That would give us 16 megs of ramdisk without taking up any more of the atari's adress space, and also maintaining the 2-byte register format.

 

This should only require 2 more multiplexed adress lines to the SIMM.. There are already enough extra chip footprints on the existing board desgin to do this. The only downside is that 16meg 30pin SIMMS are rare as hell..

 

I realize that you're probably trying to use the current PCBs but what about using a 72 pin SIMM or multiple 30 pin SIMMS (I thought 4 meg SIMMS were rare as hell, I didn't think anything bigger existed). Could a daughter board be attached without a great deal of trouble?

 

If I do release a daughterboard, it will be static RAM based.. Extra simm sockets is really not a very good option.. especially if you expect this thing to fit in an MIO case. 72pin SIMMS are 32bit data-bus, and would need the extra logic to handle that... A 4,8, or 16 meg 30pin SIMM would just need a few more wires on the back of the board, a couple ICs (which theres already room for), and a firmware change.

 

But Im producing these first 22 as exact MIO replacements. There will be firmware upgrades for it... Something has GOT to be done about the 256byte sector limitation.. And there may be daughterboard upgrades in the future.. But for now.. I am selling these things as STOCK MIOs.. Guaranteed to work 100% exactly like a 1-meg ICD MIO.. And thats all Im officially claiming at the moment.. After all of this is done, you guys have your MIOs in your hands, and all of this is "off my plate" so to speak, then we can start talking about upgrades to the design.

[danwinslow]

ON the subject of 16MB simms, would something like this work?

http://www.memoryx.net/apl30p16.html

 

Also, Ken, I was wondering if you still wanted to do that little SBC interface when all this settles down. I

[ataridano]

 

I realize that you're probably trying to use the current PCBs but what about using a 72 pin SIMM or multiple 30 pin SIMMS (I thought 4 meg SIMMS were rare as hell, I didn't think anything bigger existed). Could a daughter board be attached without a great deal of trouble?

 

But Im producing these first 22 as exact MIO replacements. There will be firmware upgrades for it... Something has GOT to be done about the 256byte sector limitation.. And there may be daughterboard upgrades in the future.. But for now.. I am selling these things as STOCK MIOs.. Guaranteed to work 100% exactly like a 1-meg ICD MIO.. And thats all Im officially claiming at the moment.. After all of this is done, you guys have your MIOs in your hands, and all of this is "off my plate" so to speak, then we can start talking about upgrades to the design.

 

I wasn't trying to imply that the first 22 should be modified in any way, just a thought for the future production. On the hard drive issue, I've never heard a clear answer to what the limitations are. In other words, what drives support 256 byte sectors? Can I low level format a newer drive to work? Can I just use half of a sector on a newer drive? Can I use half a sector of a newer drive with a slight mod to the firmware? Let's face it, if I could only use half the capacity of a hard drive, I'd still never run out of space. At this point the ram drive and serial port are what I'm looking forward to, but being able to use 512byte sectors would let me attach my CD-ROM!

[MEtalGuy66]

I wasn't trying to imply that the first 22 should be modified in any way, just a thought for the future production. On the hard drive issue, I've never heard a clear answer to what the limitations are. In other words, what drives support 256 byte sectors? Can I low level format a newer drive to work? Can I just use half of a sector on a newer drive? Can I use half a sector of a newer drive with a slight mod to the firmware? Let's face it, if I could only use half the capacity of a hard drive, I'd still never run out of space. At this point the ram drive and serial port are what I'm looking forward to, but being able to use 512byte sectors would let me attach my CD-ROM!

 

 

The plan at the moment (and this may change) is to fix the MIO firmware.

 

The main issues Id like to see adressed in a firmware update are 1) 512byte sector compatability.. 2)eliminate existing bugs in the menu program, and 3)if possible, add a partition list/assignment screen similar to what the black-box has.

 

some of this may be done in the form of executables run from disk, rather than included in the on-board firmware.

 

But, all of this, really is the topic of a future discussion.

[danwinslow]

On the subject of 16MB simms, would something like this work?

http://www.memoryx.net/apl30p16.html

[MEtalGuy66]

On the subject of 16MB simms, would something like this work?

http://www.memoryx.net/apl30p16.html

 

Yep. Thats a 16meg 30-pin SIMM. FPM (fast page mode) which is fine.

 

But once again... I am FINISHED with the DRAM interface for this run of boards. I am concentrating on assembly now. If we decide to do firmware support for larger DRAM configurations, it will be a future upgrade/mod..