pnr

I'd be intersted to take a look at that manual. If someone locates it, please post a link

Hi Fabrice, The TI99/5 appears to use a TMS9500 processor, a TMS9995 derivative. Karl Guttag (the 9995 designer) does not recall such a derivative version ever being made, but is was long ago and he does not exclude the possibility that the home computer division used a different number for the same chip. Do you have a photograph of the actual on-chip markings? I'm not doubting you, but would like to see if I can dig up more info on this chip. By the way, here is a memo from the home computer division asking for revisions to the tms9995: http://msx.hansotten.com/uploads/msxdocs/1982-03%20Home%20Computer%20Request%20for%20Mods%20to%209995%20and%209918.pdf

Okay, colour me interested. There are a few pieces of Marinchip M9900 documentation here: http://quantums.info/cortex/MPE%20documentation/ (CPU board, RAM board, I/O board). Is it that? If it is something other, I'm willing to do the scanning. However, I'm based in Europe.

What Marinchip documentation is that? Is it different from the MDEX documentation available at: http://www.powertrancortex.com/documentation.html ??

I think the documents you refer to were posted in the yahoo group some 5 years ago: https://groups.yahoo.com/neo/groups/ti99-4a/conversations/topics/72673 https://groups.yahoo.com/neo/groups/ti99-4a/conversations/topics/72672 The '673 document is the main specification, the '672 document is an addendum/errata to the former. It says that once upon a time Microsoft had a reference implementation in C for this spec, and also that the spec should be complete enough to write one from scratch. Has anyone ever attempted a disassembly & analysis of the Multiplan cartridge ROM? This p-code looks quite well done, allowing substantial programs in little memory. It has a single 64K data space for global data and the stack, and an essentially unlimited segmented code space: the code is divided up into relocatable "segments" that are paged in and out as needed. Also, the p-code looks very tight, packing many C operations in a single byte. If there is a reimplementation of this, and if someone has an old Microsoft C compiler (i.e. one of the DOS 16-bit compilers) that still supports generating this p-code, we would have another great tool for writing new software.

Perhaps this photo helps. This board has a socket (strip) fitted for the F18A. The CF Card breakout board comes about as high as a socketed DIL package.

If you do find it, I would be highly interested in a copy. It sounds like that document has documentation for the p-code part of Microsoft's "revenue bomb" C compiler (see here for some background). I think this p-code interpreter later evolved into the Visual Basic runtime, but that is speculative. Having a re-implementation of this bytecode interpreter, combined with old versions of Microsoft C that still included "cs" may lead to an interesting compiler option for the TI (it is said to create very tight binaries). By the way, the fathers of this compiler, Charles Simonyi and Richard Brodie, are key figures in the microcomputer revolution of the 80's, driving the development of what eventually became Microsoft Office -- starting with defining the very concepts of it while at Xerox' PARC labs back in the 70's. Their wikipedia pages make interesting reading.

The MiniCortex I'm designing has an F18A. The MiniCortex is a eurocard sized SBC with a 9995 CPU and roughly modeled on the Powertran Cortex (schematics). It started out as an extended version of Stuart's breadboard design for the 9995.

How about a bit of history? The TI990 was designed as a successor to the TI960 and TI980 computers. The TI960 was a process/production control computer, quite similar to what we would now call a PLC. Its purpose was to interface to all the sensors and actuators of an industrial plant, and that is where the bit addressability comes in handy. A brochure for the TI960 is here: http://bitsavers.informatik.uni-stuttgart.de/pdf/ti/960/960Flyer.pdf The CPU would interface to multiple cages with I/O cards through a simple 15 wire bus (12 address, cruin, cruout, cruclk). The TI990 operated two busses that were physically separate, the CRU bus (to communicate with industrial I/O cards) and the TILINE bus (for memory, disk controllers, etc.). As mentioned in an earlier post, the TMS9900 multiplexes the two buses onto shared pins. Up to 7 I/O cages could be hooked up, with up to 24 cards in each cage. A card typically provided 32 I/O's. A description of how TI envisioned the TI990 series can be found here: http://bitsavers.informatik.uni-stuttgart.de/pdf/ti/990/945250-9701_990_Computer_Family_Systems_Handbook_3ed_May76.pdf Section 2.1.10 has an extensive explanation of the above. The TI960 heritage was also one of the considerations in choosing the workspace concept for registers, or so it seems.