Jump to content

MEtalGuy66

Members
  • Content Count

    2,806
  • Joined

  • Last visited

  • Days Won

    1

MEtalGuy66 last won the day on October 17 2009

MEtalGuy66 had the most liked content!

Community Reputation

543 Excellent

About MEtalGuy66

  • Rank
    River Patroller
  • Birthday 10/19/1973

Contact / Social Media

Profile Information

  • Custom Status
    If it aint broke, fix it anyway!
  • Gender
    Male
  • Location
    Houston, TX, USA
  • Interests
    ATARI XL/XE hardware repair, ICD Multi I/O reproduction/development, SpartaDOS, MAC/65, BASIC XE, ATARI TELNET BBSes and related hardware, AMIGA 1000/500/500+, preservation of the 5.25" floppy as a standard for 8-bit computers.

Recent Profile Visitors

26,023 profile views
  1. Aww Hell.. I guess I'll take a couple..
  2. Just like the title says. http://www.rasterline.com/cmo.pdf I found this under a stack of printouts when I was cleaning out some junk. I'm sure someone else has probably already scanned this but no idea how to find it so here it is again. We should have a section for historical media.
  3. Not even remotely the same thing.
  4. God, this question has been asked a million times in here. I bet I've written 50 pages on it personally.. The 1400XL and 1450XLD machines were the last to have a buffered data bus between the CPU and the hardware. The original PBI expansion bus and the 1090XL both depended on this design feature/characteristic in order to have some semblance of stable operation. When it came time to actually bring machines to market, in the early 80s, many "cost cutting measures" were implemented in the design before the actual production machines (1200xl,600xl,800xl) came to market. One of these was the REMOVAL of the buffers on the data bus. Instead, all hardware bus traffic would be directly synced by the PHI2 signal from Sally. This is fine as long as your bus capacitance is finite and known.. Which it can not be, when there's a possibility of plugging many devices directly onto the bus, as in the case of the PBI (and cartridge too, actually). So what we ended up with is a machine that, although the physical connector was still there, could never run an architecture of parallell bus expansion reliably. Atari essentially made a decision to abandon the possibility of bus expansion in favor of getting the XL series to market at a price point that they felt the market would bear.. Sad but true.. This is why the only device ever actually sold by Atari to utilize the PBI connector was the 64k upgrade for the 600XL. Aftermarket developers, however, chose to utilize the PBI bus for various interfaces such as the Supra, ICD MIO, and CSS Black Box.. But if you know anyone who has owned these, they usually require "fine tuning" of the bus timing on the machine in order to operate with any degree of stability. In fact, the more things you hang off of the data bus in general, the more phi2-to-bus timing gets skewed by increased capacitance (and thus propagation delay), and it will cumulatively cause the machine to become irrattic/unstable/unoperational unless appropriate hardware measures are taken to compensate and bring the bus timing back into valid sync with PHI2. This includes internal expansions that plug into chip sockets, cartridge based expansions, and PBI devices. The more crap you hang off the bus, the worse it gets. And once you get a heavily expanded system like that "tuned" for stable operation, any major changes (such as removal of a cart or PBI device) often throw it "out of whack" the opposite way because now you've reduced bus capacitance/propagation delay. So you've got to "retune" again. This "tuning" can be done in a variety of ways. These range from the simple addition of capacitors on bus lines to slightly increase delay, to shortening/lengthening of entire bus interconnect cables, to complex compensation circuits. MANY hardware people in this hobby have devoted untold hours to this problem. Unfortunately, short of redesigning the XL/XE machine spec, there is no universal fix. And without that, a 1090XL like device, while not impossible, is really "asking for it" in terms of installation specific troubleshooting and "hair pulling".. Whew! I hope this is the last time I have to explain that. But it probably wont be.. Short answer to your actual question: regardless of which type of interconnects you use, internal, external chain, external back-plane ala 1090xl... For extensive parallel bus expansion, you need reliable bus timing.. The original 1400xl/1450xld designs had this. The apple II has this.. Machines like the production atari XL/XE, the commodore 64, etc.. Do not..
  5. That's a 16meg MIO. The protoboard has the additional logic for the addtional RAM adressing. It works, but we never made a ROM that supports it. We were instead going to include the 16meg expansion in a much larger scale "piggyback expansion" that added a whole bunch of extra features.. But that never made it past prototype either. I think WareRat has that protoboard somewhere.. Anywayze.. This MIO is also the very first one we got working. It has all the hacking and splicing under the board that got corrected in the second board revision.
  6. Ok. Well, I was considering making some more.. But Since Faicuai doesn't approve, I guess I won't.
  7. No one is talking about "hacking up" anything..
  8. Your browser must be really fubar.. I just checked it and its the same as its been for the last decade or so..
  9. It's been a long time. Warerat might know the answers to those questions. But, does it really matter? The ROM posted on my site is definitely the latest one intended for public release. Of that, you can be sure. If there is a "later" ROM, it's one that was given to someone as a special purpose tweak, and they leaked it out.
  10. How much Charmin is this one worth?
  11. I have 2 of them sitting right. Here. I was gonna sell them to Curt Vendell. But if you'll buy out his rights, Id be glad to price-gouge them to the highest bidder..
  12. Wow. None of the old schoolers care to chime in here? Anywayze, I have a few things further to add. I noticed that StGuild said in an earlier post: Is it a Toggle-switch? I assumed it was a momentary push-button. If it is in fact a toggle switch, then it has something to do with the way the PIA bits are used to address the expansion. One popular "switch" of this sort that would be connected in such an upgrade was to change between "compyshop and rambo XL" similar banking schemes. Another was a "switch" to give back 1 bit of PIA control, reducing extended ram to 192k, but allowing separate ANTIC and CPU access to the currently selected extended bank. This is sometimes called "100% 130xe compatability mode". At any rate, what you should do is download SatanTronic's XRAM prorgam and see which banks show up with various switch positions. This Demo, known as VBLITZ or VIDEO BLITZ used to be the definitive test of 130XE ANTIC Extended Video Mode. (You have to unarc it first) Lastly, here's a picture of a REAL 1meg upgrade, like we used to do back in the 80s.. Looks like it might have been done by the same guy who did your 320k. Notice he has not only replaced the extended bank with 256k DRAMs, but he's piggybacked an additional 3 banks of chips and hand-wired the address lines as necessary. I have forgotten what the various switches do, but you can bet they have to do with banking, compatability, etc. To get enough PIA bits for 1meg, you have to give up Internal BASIC, SELF TEST, Extended video, etc. Scott Petersen was a hardware guy back in the 80s who came up with these upgrades and published them in step-by-step articles which would be distributed as text files on BBS systems. Most Atari user groups had a "hardware guy" that could install these types of mods for people. Petersen did the original 320k article, followed by a 576k, and finally a 1088k... Somewhere, I have all of the original text files, but I'm sure they are available in many places on the web. Oh well. Just thought I'd reminisce a bit, about the way we USED to do things, since STGuild brought it up.
  13. That's not a 1meg XE.. That's a 320k.. How do I know? Only 2 additional PIA bits are used by that expansion (only 2 wires going to the PIA chip). The 130xe used 2bits for extended ram in stock configuration.. Adding 2 more gives you 16 (2^4) banks of 16k.. 16 x 16 = 256... So 64k base ram plus 256k extended.. Thats 320k.. Very popular upgrade.. There's also the fact that there's only 1 bank of (256k)DRAM chips in the extended bank. They did make 1meg DRAMs but no one used them for homebrew atari 8 bit ram expansions because they require additional wiring to connect, and even more additional circuitry for refresh because ANTIC will not refresh that many address bits of DRAM by itself.. What's under the black tape, you ask? Probably a 74HC86.. You see the momentary push button on the back of the case? Hold that button and hit reset to cold-reset the machine without wiping out the contents of the extended ram.. You have to boot back up and use a special ramdisk handler to reconfigure the ramdisk without initializing it, but you can cold boot the machine and still have your data in ram.. Anywayze.. What you have there is a "Scott Petersen 320k upgrade", with a "Bob Wooley freezer switch" mod added.. It looks fine to me.. make sure there's no broken wires, and no exposed wires touching anything metal.. Put it back together and enjoy.. There are plenty of demos that use the extra ram, and you can use it as a 256k ramdisk in both SpartaDOS X, and disk based versions of SpartaDOS.. If I was you I'd either (a) leave it alone and enjoy your 320k XE... Or (b) Buy an "Ultimate 1 Meg" Expansion from Lotharek and find a competant hardware guy to put it in for you. Regards, Ken Jones Metalguy66
  14. _The_Doctor__, wtf is the "almost rice" version? You really should keep your mouth shut on topics you know nothing about. The "blue" wires on the back of the MIOs had several functions and it doesn't matter which side of the PCB they were on. I've seen ICD put them on either side.. top or bottom. One was the deletion of the 12v power circuit from the design which happened fairly early on in the production history of MIOs, so most of them were built this way. The second was a propagation delay for the highest order DRAM address line. It used a few spare gates in one of the ICs to add ~10-20ns of delay to that line so it would more closely line up with the others in the DRAM access timing. Almost Rice (Tuon Ho,) is a personal friend of mine.. I assure you he had nothing to do with MIO firmware development. WareRat is the man responsible.. You should get your shit straight before flapping your jaw. Somewhere, I've got 1.2 and 1.3 ICD MIO EPROM binaries and partial source code. I might get persuaded to dig them up if someone's interested.. But not tonight.
  15. MEtalGuy66

    MEtalGuy66

×
×
  • Create New...