video upgrade?

[ClausB]

Progress!

 

I took a 20ns 32KB SRAM from an old '486 and plugged it into an even older OSS cart, added a couple of gates for the write strobe, and tried it on my 800XL. It works! Using the 4-bit control register on the cart, I can switch between 4 banks of 8K. So now I have a small RAMcart, but I still have to add the video generator. I'd like to put it into a PAL but it might not fit. Can anyone suggest any free CPLD software and a cheap programmer?

[candle]

xilink web pack with xc95xx familly?

some devices are in plcc84 packages - should be easy enought

programmer schematics are free and avaivable from xilink

[HiassofT]

Hi Claus!

 

Can anyone suggest any free CPLD software and a cheap programmer?

Altera, Lattice and Xilinx all offer free development software (Quartus Web Edition, ispLever Classic/Starter, Xilinx WebPack). IMHO they are all a PITA, so choose the manufacturer/software that hurts you the least :-)

 

I haven't tried Quartus for quite a while, but I have both ispLever and Xilinx installed on my PC (Xilinx even offers a free Linux version). Be prepared to have some 20GB of free harddisk space and a fast internet connection: The Xilinx download is ~2GB (!) plus another ~1GB for the "service packs". OTOH ispLever Classic is a really nice, slick package, it's only a ~1GB download :-)

 

OK, enough ranted, both devkits are usable, both take some time to get used to them, and there are tutorials available/included so you should know the basics after a few hours. There are some things I prefer in the Lattice software, and some other things I prefer in the Xilinx software - so no clear winner here.

 

Another important thing is of course the features of the CPLD. At the first glance there are no big difference between Lattice iM4A5 and XC95xx, but there are some subtle features that might come handy from time to time: Lattice M4A5 has programmable pull-ups on the input (XC95xx don't offer them) and some of the iM4A5s (like M4A5-64/32) support dedicated input-registers/latches. Especially the input-latches were really great to solve timing problems with the Atari: just latch the input signals (address lines etc) when PHI2 is high and you don't have to care about broken Ataris where address/data lines become invalid before the falling edge of PHI2. But beware: not all M4A5s have this feature, with some of them you have to use some of the internal registers to latch inputs.

 

Programming the CPLDs is also very easy. You don't need a special programmer, all devices are in-circuit programmable with a simple JTAG cable. You can built such a cable by yourself, the simplest one is just 4 wires (plus GND) connected to the PC parallel port (OK, it's better to add some buffers/line drivers plus resistors in series to protect your parallel port, but just 4 wires also works).

 

JTAG programming software is also included in the Lattice/Xilinx packages, but - of course - you need to use the Lattice JTAG cable for the Lattice software, and the Xilinx JTAG cable for the Xilinx software (no, they aren't compatible - of course :-). Since I don't like this, and my Xilinx cable is currently broken, I use the Xilinx software to create a SVF programming file and then use urjtag in Linux to program the Xilinx CPLDs using my Lattice cable. Works great :-)

 

so long,

 

Hias

[+warerat]

If your design is something that would only need at the most around 20 I/Os and a few registers, it's probably easier to stick with SPLD like GALs. In that case WinCUPL is available for free but targets Atmel devices. Not the greatest software, but good enough to get something done. If your device programmer doesn't handle them, there's a few plans out on the web to make standalone GAL programmers.

 

If your design warrants moving to CPLD then you can pick Altera (Quartus), Xilinx (ISE Webpack), and Lattice (ispLever). I only have personal experience with Altera and Xilinx. As Hias mentioned, the software will have a subtle learning curve. I thought the Altera and Xilinx software was similar. Only thing I found annoying about the Altera software is that while it is free software, it requires them to issue you a FlexLM license periodically to keep it running. And yeah, the Xilinx software is bloaty, but I like it now. These all get programmed through JTAG and there's documentation out there on making adapters for the parallel port.

 

Most of pricing for the 5V-only CPLD devices are pretty steep when you can find them (compared to their 3.3V cousins). I wouldn't recommend those except for prototyping and convenience.

[ijor]

Only thing I found annoying about the Altera software is that while it is free software, it requires them to issue you a FlexLM license periodically to keep it running.

 

Not anymore.

[HiassofT]

Hi warerat!

 

I only have personal experience with Altera and Xilinx. As Hias mentioned, the software will have a subtle learning curve.

Do you know if there's something like a post-fit simulator in the Xilinx software? IIRC either Altera or Lattice included one (but I could be wrong, it was some 5 years ago when I used it - or think I was using it). IIRC you could provide a set of input stimuli and then get a plot of the output signals. Nice thing (again, IIRC) was that it also simulated the internals of the CPLD (including placed logic) and you could see all glitches/spikes in the output - useful to analyze combinatorial logic where some signal paths were a little bit longer and could therefore result in a ~10ns glitch.

 

So far I only looked at the "Timing Analyzer", but it only reports that a signal will be valid some X ns after some other signal, and not what's happening between the minimum pad-to-pad delay and time X.

 

Maybe I just haven't found it, maybe I'm using a completely wrong approach - I'm still learning how to use the Xilinx tools.

 

Only thing I found annoying about the Altera software is that while it is free software, it requires them to issue you a FlexLM license periodically to keep it running.

This is (unfortunately) also true for the Lattice software. And I'm not 100% sure if a new license is guaranteed to work with an older version of the software (maybe you need to also install the current software version). I'll have to check this some time, the current Lattice software is unable to fit my TurboFreezer logic into a M4A5-64/32, but the software back then (IIRC version 4) worked fine...

 

so long,

 

Hias

[ijor]

Do you know if there's something like a post-fit simulator in the Xilinx software? ... So far I only looked at the "Timing Analyzer"...

 

Dynamic timing simulation is obsolete for most purposes. Static timing analysis is superior in almost every concept. You can do the former if you insist, but it would rarely be useful and helpful.

 

If your design can't afford glitches at the output, then you shouldn't depend on combinatorial logic and register the output. Trying to solve this with timing simulation is the wrong idea.

 

Both Altera and Xilinx (and others) have some nice papers about timing simulation and analysis.

Edited March 22, 2009 by ijor

[HiassofT]

Hi ijor!

 

Dynamic timing simulation is obsolete for most purposes.

I was guessing this, and I realized (and think also understood) the reasons why most people switched to registered logic.

 

If your design can't afford glitches at the output, then you shouldn't depend on combinatorial logic and register the output. Trying to solve this with timing simulation is the wrong idea.

I know this is not the perfect solution, but currently I don't have an idea how I could move from combinatorial to registered logic. Some 5 years ago I searched for clock multipliers (so that I could do registered logic at, for example, 4 times Atari clock), but none of the clock-multipliers would work down to 1.79MHz input clock (I need to search again, maybe some are available now).

 

Currently I'm working on yet another SRAM upgrade using a XC9536 and had intermittent errors with a BS62LV4006PCP55. It seems to react allergic on short glitches on the CS/OE/WR lines (most likely at the beginning and/or end), but it's this really nasty kind of Heisenbug that only shows up once in a while...

 

So I was trying to make the logic glitch-free, dynamic timing analysis already helped me once to track down an issue that I missed, but now I (hopefully) solved it by thinking: My current solution introduces intermediate, internal CE/OE/WE signals that I prevent from being removed by the optimizer using an "attribute KEEP", and then add another process to gate these signals with PHI2 (or PHI0 and PHI2) to create the CE/OE/WE signals for the RAM. I think I should have done this right from the beginning, but, well, I'm not an expert in CPLD design and I guess these are the mistakes you have to make once and then learn from them :-)

 

Both Altera and Xilinx (and others) have some nice papers about timing simulation and analysis.

Thanks for the info! I'll read them and then (hopefully) be a little bit wiser than now!

 

so long,

 

Hias

[+bob1200xl]

I use ATMEL's WinCUPL (free) on an EETools ChipMaxII programmer ($600). The ATMEL software only compiles to their chips, but that includes the Atari PALs and some really useful CPLDs. The ChipMax does just about anything. Both of these tools are actively supported.

 

Bob

 

 

 

Progress!

 

I took a 20ns 32KB SRAM from an old '486 and plugged it into an even older OSS cart, added a couple of gates for the write strobe, and tried it on my 800XL. It works! Using the 4-bit control register on the cart, I can switch between 4 banks of 8K. So now I have a small RAMcart, but I still have to add the video generator. I'd like to put it into a PAL but it might not fit. Can anyone suggest any free CPLD software and a cheap programmer?

[awace]

Progress!

 

I took a 20ns 32KB SRAM from an old '486 and plugged it into an even older OSS cart, added a couple of gates for the write strobe, and tried it on my 800XL. It works! Using the 4-bit control register on the cart, I can switch between 4 banks of 8K. So now I have a small RAMcart, but I still have to add the video generator. I'd like to put it into a PAL but it might not fit. Can anyone suggest any free CPLD software and a cheap programmer?

the last number on the chip should not be a 20 it shoud be a 10 as in 10 nano.......!!!!!!!!!!!!!!!!!

[ijor]

Some 5 years ago I searched for clock multipliers (so that I could do registered logic at, for example, 4 times Atari clock), but none of the clock-multipliers would work down to 1.79MHz input clock... My current solution introduces intermediate, internal CE/OE/WE signals that I prevent from being removed by the optimizer using an "attribute KEEP"...

 

I'm not sure I understand exactly what was your solution, but it doesn't sound too correct. "KEEP" is mostly a debugging and simulation tool. If your design depends on it, then it hints that something was probably wrong.

 

The way I would approach this would be to use the Atari clock signal as data, and not as a clock. Use your own oscillator as the clock for the modern logic. Your fast modern (or semi-modern) logic should have no problems in sampling the Atari clock signal. You just must be careful on how you synchronize it.

 

The only problem with this approach is that it would probably increase slightly the size of your design. So if you are already struggling to fit it in a given part, then it might not fit. And of course that you need to consider as well, the addition of the external clock to the board.

[+bob1200xl]

The ATMEL ATF750 is a 24 pin DIP (.3in) with 22 active pins - up to 22 inputs (for write-only memory applications) and 10 outputs. Each output can also support a 'buried' latch, giving you 10 more logic blocks. Nice thing about these is that you can move the same code up into much larger arrays, like 64 or 128 nodes. Just the ATF750 should be adequate.

 

Bob

 

cheapest programmer I know is to send me the code and I'll send you an IC...

 

Progress!

 

I took a 20ns 32KB SRAM from an old '486 and plugged it into an even older OSS cart, added a couple of gates for the write strobe, and tried it on my 800XL. It works! Using the 4-bit control register on the cart, I can switch between 4 banks of 8K. So now I have a small RAMcart, but I still have to add the video generator. I'd like to put it into a PAL but it might not fit. Can anyone suggest any free CPLD software and a cheap programmer?

[HiassofT]

I'm not sure I understand exactly what was your solution, but it doesn't sound too correct. "KEEP" is mostly a debugging and simulation tool. If your design depends on it, then it hints that something was probably wrong.

This is my current solution to avoid glitches in a combinatorial design. I wanted to make sure that there were no glitches from, for example, the falling edge up to the rising edge of /CE introduced by the optimizer. It's similar like in the good old days with TTL logic: do all the combinatorial stuff and at the very end gate it with PHI2.

 

I'm not sure if this is really the right way to solve it, but it seems to work and so far I haven't discovered a better way. I'm still in the learning phase, so every hint is welcome.

 

A more detailled explanation: it's not only a single "clock" (which is mainly used in combinatorial logic), but 2 "clock" signals. For read operations I gate OE with PHI2, for write operations I gate WE with "PHI0 AND PHI2". My problem now is that I'd really like to keep the hierarchy (i.e. the gating with PHI0 AND PHI2 at the very end), and preventing the optimizer from shuffling around logic terms (for example it could think that taking "some logic AND PHI2" from macro cell X plus "some other logic" works fine and saves some space - but it destroys the hierarchy and introduces possible glitches).

 

The way I would approach this would be to use the Atari clock signal as data, and not as a clock. Use your own oscillator as the clock for the modern logic. Your fast modern (or semi-modern) logic should have no problems in sampling the Atari clock signal. You just must be careful on how you synchronize it.

Yes, this is a possible solution. Back then I also thought about it, and this is also how the original TurboFreezer with the 82S105 worked. A solution would have been to use a PLL to lock onto the Atari clock, but at 4 or 8 times the frequency (an unsynchronized oscillator could cause problems when synchronizing this clock with the Atari clock inside the CPLD if it drifts too much). I wanted to avoid the troubles of creating and designing a PLL (I read a lot of datasheets and appnotes, but still I'm not really familiar with PLLs), so I thought a ready made clock multiplier (basically a PLL on a chip) would have been nice.

 

The only problem with this approach is that it would probably increase slightly the size of your design. So if you are already struggling to fit it in a given part, then it might not fit. And of course that you need to consider as well, the addition of the external clock to the board.

Size is not a problem in this case, but I'd really like to try to solve it with combinatorial logic in a CPLD. I'm just struggling with the synthesis tools, or maybe I'm using them in the wrong way...

 

so long,

 

Hias

[ijor]

This is my current solution to avoid glitches in a combinatorial design...

 

I'm following up on PM. We are going too off-topic. Sorry about.

[ClausB]

Thanks to all for laying out my options. There's a lot to consider and more to learn.

cheapest programmer I know is to send me the code and I'll send you an IC...

Thanks for the offer! I might just take you up on it.

[drac030]

In meantime, if anyone has VBXE, here is a SpartaDOS X driver that installs as "S2:" in the OS and allows to use the four new display modes to be played with under BASIC:

 

http://drac030.krap.pl/vbxe_s.arc

 

Examples (written in Turbo BASIC XL) and description included.

[drac030]

Again, if anyone is interested, here are some snapshots taken from the VBXE display (nothing special, just the output of the Turbo BASIC XL examples for the above driver):

 

1) STDRES.TXL, first drawing, 320x192/256 colors, standard Atari palette:

 

 

2) same program, same resolution & palette, second drawing:

 

 

3) same program, same drawing, only slightly modified loops to produce solid triangles:

 

 

4) same program, third drawing:

 

 

5) same drawing in grayscale palette instead of 256-color (STDGRAY.TXL):

 

 

The drawing speed under Turbo BASIC XL is ~2.5 times greater than in GRAPHICS 8.

 

All of the pics have been taken from a real Atari with VBXE and saved as 256-color BMP files, which have been subsequently converted to PNG on a PC.

Edited March 27, 2009 by drac030

[Mathy]

Hello Drac030

 

You don't have to convince me (us?) that I (we?) need one. You have to convince somebody to make and sell them.

 

greetings

 

Mathy

[drac030]

This is what I am doing

[Rybags]

Can VBXE do page-flipping on a per-frame basis?

 

I reckon if it can, then we should be able to double the vertical resolution with interlacing, provided it does the GTIA emulation correctly.

[drac030]

Can VBXE do page-flipping on a per-frame basis?

 

I reckon if it can, then we should be able to double the vertical resolution with interlacing, provided it does the GTIA emulation correctly.

 

So far no inaccuracies in GTIA emulation have been detected, so I think that any tricks that work on ANTIC/GTIA should also work on ANTIC/VBXE. But the 256-color modes above have nothing to do with GTIA or ANTIC, these are completely produced by the VBXE, with own DL etc. I am not familiar enough with the XDL to tell you now (without consulting the manual), if it does page flipping. But even if not, this could be certainly done using the blitter, which is fast enough to copy 60 KB from one place to another in less than half of a frame, and it does not hog the CPU while copying.

[Rybags]

These modes are overlayed though aren't they?

 

Or at least does it still rely on Antic to give it HSync and VSync timings?

[drac030]

They can be overlayed, yes. And yes, it gets sync signals from ANTIC.

[ClausB]

Well, so why am I wasting my time then?

[+Larry]

Well, so why am I wasting my time then?

 

Because "the bird is still in the bush"

 

-Larry