+Lee Stewart Posted June 11, 2021 Share Posted June 11, 2021 5 hours ago, GDMike said: Lee, is your general replacement of VMBW and VMBR,VSBW and VSBR, EDITOR assembler routines for reading and writing to VDP ram, what you recommend in the examples above? Or do you have or use something different for general use ? And what sorta savings does it do if I use them instead of the EA version? As Rich mentioned, the E/A VMBW, etc. are invoked with BLWP, which is difficult to do with RXB because extended RAM is not required and there is not enough room in scratchpad RAM for both the extra registers and the row buffer I wanted—one or the other, but not both. When you use BL branching, you must worry about register use and saving returns if BLing more than one level. I generally use my own VMBW, etc. (practically identical to the E/A versions) in fbForth, except when I want very fast transfers. Then I waste the space for faster inline code. BL/RT is a good bit faster than BLWP/RTWP. You do lose a little of that advantage when you must save/restore returns for multiple levels, but it is still faster. You also need to ensure that interrupts are disabled when accessing VRAM. I presume that Rich has handled that prior to calling the roll routines. That is why I did not use LIMI instructions in the above code. ...lee 1 2 Quote Link to comment Share on other sites More sharing options...
+Lee Stewart Posted June 11, 2021 Share Posted June 11, 2021 7 hours ago, RXB said: Your use of FAC instead of VDP >03C0 for only 32 characters is pretty minimal for increase in speed overall. I think you will find the increase in speed is not minimal. I am copying 32 characters with only one VDP-Write-Address set of instructions. You are doing 32 of those, once for every byte you read/write from/to VRAM. That is certainly much slower. ...lee 2 Quote Link to comment Share on other sites More sharing options...
+TheBF Posted June 11, 2021 Share Posted June 11, 2021 6 hours ago, RXB said: Oddly all of these are built into the XB ROMs but they do not have the same names and it is strange that no one before has utilized them as space saving? I mean look at how much space you could save in Lower 8K using them! I didn't know these were also in ROM. I suspect it would awkward to use them if you are not in the GPL workspace. How do I find them to take a look? 1 Quote Link to comment Share on other sites More sharing options...
RXB Posted June 11, 2021 Share Posted June 11, 2021 2 hours ago, TheBF said: I didn't know these were also in ROM. I suspect it would awkward to use them if you are not in the GPL workspace. How do I find them to take a look? RXB ROMs.zip 3 1 Quote Link to comment Share on other sites More sharing options...
RXB Posted June 11, 2021 Share Posted June 11, 2021 Ok have the ROM3 set up and looks great, still have to write the GPL to make it work. **************************************************************** AORG >6000 TITL 'RXB ROM3' UNUSED DATA >0000,>0000,>0000,>0000 DATA >0000,>0000,>0000,>0000 **************************************************************** * XML table number 7 for RXB ROM3 - must have * * it's origin at >6010 * **************************************************************** * 0 1 2 3 4 5 6 DATA RROLL,LROLL,UROLL,DROLL,>0000,>0000,>0000 * 7 8 9 A B C D DATA >0000,>0000,>0000,>0000,>0000,>0000,>0000 * E F DATA >0000,>0000 **************************************************************** * XML table number 8 for RXB ROM3 - must have * * it's origin at >6030 * **************************************************************** * 0 1 2 3 4 5 6 7 DATA >0000,>0000,>0000,>0000,>0000,>0000,>0000,>0000 * 8 9 A B C D E F DATA >0000,>0000,>0000,>0000,>0000,>0000,>0000,>0000 * F **************************************************************** * Start of routines * **************************************************************** * Windy XB routines from previous Assembly adapted **************************************************************** * direction = U (up), D (Down), L (Left), R (Right) * repetition = repeat number times * string = string or string variable to display just like PRINT **************************************************************** * CALL ROLL(direction,...) * CALL ROLL(direction,repetition,...) * Assembly roll the screen like a drum with number of times also **************************************************************** * XML MVDN (MV05 for VDP) (VDP to VDP) * ********************************************************** * CALL RROLL(direction,repetion,...) * ************************************************************ RROLL MOV R11,R8 * save return address LI R2,24 * ROW counter LI R3,31 * 31 right edge Screen Address LI R5,>03C0 * Buffer for 24 characters LI R1,1 * 1 Byte BL @LRLP1 * Move IT * Buffer has 24 far right characters LI R2,24 * ROW counter CLR R3 * Screen address LI R5,1 * Destination BL @LRLP2 * Move IT * Moved all on screen 1 right LI R2,24 * ROW counter LI R3,>03C0 * Buffer for 1 character LI R5,1 * 1 left edge Screen Address LI R1,1 * Get 1 Byte BL @LRLP3 * Move IT B *R8 * RETURN ************************************************************ * CALL LROLL(direction,repetion,...) * ************************************************************ LROLL MOV R11,R8 * save return address LI R2,24 * ROW counter CLR R3 * 0 left edge Screen Address LI R5,>03C0 * Buffer for 24 characters LI R1,1 * 1 Byte BL @LRLP1 * Move IT * Buffer has 24 far left characters LI R2,24 * ROW counter LI R3,1 * Screen address CLR R5 * Destination BL @LRLP2 * Move IT * Moved all on screen 1 left LI R2,24 * ROW counter LI R3,>03C0 * Buffer for 1 character LI R5,31 * 31 right edge Screen Address LI R1,1 * Get 1 Byte BL @LRLP3 * Move IT B *R8 * RETURN ************************************************************ LRLP1 MOV R11,R9 * save return address LRR1 BL @MIT * Move IT INC R5 * Buffer+1 AI R3,32 * Screen Address+32 DEC R2 * ROW COUNTER-1 JNE LRR1 * 0? No loop B *R9 * RETURN ************************************************************ LRLP2 MOV R11,R9 * save return address LRLPM LI R1,31 * Number of Bytes LRLPN BL @MIT * Move IT AI R3,32 * VDP address+32 AI R5,32 * VDP destination address+32 INC R1 * COLUMN COUNTER+1 JNE LRLPN * 0? No loop DEC R2 * ROW COUNTER-1 JNE LRLPM * 0? No loop B *R9 * RETURN ************************************************************ LRLP3 MOV R11,R9 * save return address LRLPO BL @MIT * Move IT INC R3 * Buffer+1 AI R5,32 * Screen Address+32 DEC R2 * ROW COUNTER-1 JNE LRLPO * 0? No loop B *R9 * RETURN ************************************************************ * CALL UROLL(direction,repetion,...) * ************************************ *********************** UROLL MOV R11,R8 * save return address CLR R3 * 0 top Sreeen Adress LI R5,>03C0 * Buffer for 32 characters LI R1,32 * 32 bytes length BL @UDLP1 * Move IT * Buffer has 32 top line characters LI R3,32 * 2nd line Screen address CLR R5 * 0 screen Destination LI R1,736 * Number of Bytes BL @UDLP2 * Move IT * Moved all on screen up 1 LI R3,>03C0 * Buffer for 32 characters LI R5,736 * Bottom left edge Screen Address LI R1,32 * Get 32 Bytes length BL @UDLP3 * Move IT B *R8 * RETURN * ********************************************************** * CALL DROLL(direction,repetion,...) * ************************************************************ DROLL MOV R11,R8 * save return address LI R3,736 * Bottom of Sreeen Adress LI R5,>03C0 * Buffer for 32 characters LI R1,32 * 32 bytes length BL @UDLP1 * Move IT * Buffer has 32 top line characters CLR R3 * 0 Screen address LI R5,32 * 2nd line Destination LI R1,736 * Number of Bytes BL @UDLP2 * Move IT * Moved all on screen up 1 LI R3,>03C0 * Buffer for 32 characters CLR R5 * Top left edge Screen Address LI R1,32 * Get 32 Bytes BL @UDLP3 * Move IT B *R9 * RETURN *********************************************************** UDLP1 MOV R11,R9 * save return address UDR1 BL @MIT * Move IT INC R3 * BUFFER+1 INC R5 * SCREEN+1 DEC R1 * COUNTER-1 JNE UDR1 * 0? No loop B *R9 * RETURN *********************************************************** UDLP2 MOV R11,R9 * save return address UDR2 BL @MIT * Move IT INC R3 * lower screen line INC R5 * upper scren line DEC R1 * COUNTER-1 JNE UDR2 * 0? No loop B *R9 * RETURN *********************************************************** UDLP3 MOV R11,R9 * save return address UDR3 BL @MIT * Move IT INC R3 * BUFFER+1 INC R5 * SCREEN+1 DEC R1 * COUNTER-1 JNE UDR3 * 0? No loop B *R9 * RETURN *********************************************************** MIT MOV R11,R10 * save return address MOVB @>83E7,*R15 * Write out read address MOVB R3,*R15 MOVB @>8800,R7 * Read a byte MOVB @>83EB,*R15 * Write out write address ORI R5,>4000 * Enable VDP write MOVB R5,*R15 MOVB R7,@>8C00 * Write the byte B *R10 * RETURN *********************************************************** * >7000 data routines * ALCEND is EA INIT * LOW1 is XB INIT * CHARS is RXB character set definitions 8 bytes each *********************************************************** AORG >1000 *********************************************************** ALCEND DATA >205A,>24F4,>4000,>AA55 DATA >2038,>2096,>2038,>217E DATA >2038,>21E2,>2038,>234C DATA >2038,>2432,>2038,>246E DATA >2038,>2484,>2038,>2490 DATA >2038,>249E,>2038,>24AA DATA >2038,>24B8,>2038,>2090 DATA >0000,>0000,>0000,>0000 DATA >0000,>0000,>0000,>0000 DATA >0000,>0000,>0000,>0000 DATA >0000,>0000,>0000,>0000 DATA >6520,>C060,>2004,>0281 DATA >4000,>130E,>C001,>0202 DATA >834A,>8CB0,>1606,>8CB0 DATA >1604,>8CB0,>1602,>C030 DATA >0450,>0221,>0008,>10EF DATA >0200,>2500,>C800,>8322 DATA >02E0,>83E0,>0460,>00CE DATA >C81D,>8322,>10F9,>C01D DATA >C06D,>0002,>06A0,>20DC DATA >C0C1,>0603,>0223,>8300 DATA >D0D3,>1361,>0983,>0643 DATA >1612,>C000,>165C,>C0C5 DATA >05C3,>06A0,>2406,>1653 DATA >05C3,>06A0,>23CA,>0204 DATA >834A,>0202,>0008,>DC74 DATA >0602,>15FD,>0380,>06A0 DATA >20F8,>10F5,>C041,>1347 DATA >0A81,>9060,>8312,>1143 DATA >0981,>C141,>0A35,>0225 DATA >0008,>A160,>8310,>045B DATA >C24B,>0643,>1634,>C0C5 DATA >06A0,>23CA,>C0C1,>06A0 DATA >2406,>112D,>06A0,>211C DATA >06A0,>23CA,>6004,>0A30 DATA >A040,>0459,>C28B,>0A51 DATA >09D1,>C201,>D120,>8343 DATA >0984,>1303,>0600,>1123 DATA >0580,>0206,>0001,>C0C5 DATA >0223,>0004,>06A0,>23CA DATA >C0C1,>0643,>05C3,>06A0 DATA >23CA,>0581,>6044,>3981 DATA >C186,>1611,>C187,>0608 DATA >15F5,>0606,>A184,>8180 DATA >150A,>05C3,>045A,>0200 DATA >0700,>0460,>2084,>0200 DATA >1C00,>0460,>2084,>0200 DATA >1400,>0460,>2084,>C01D DATA >C06D,>0002,>06A0,>20DC DATA >C0C1,>0603,>0223,>8300 DATA >D0D3,>0983,>160E,>C000 DATA >1622,>0202,>0008,>0204 DATA >834A,>C0C5,>06A0,>23CA DATA >CD01,>05C3,>0642,>15FA DATA >0380,>0643,>160F,>C000 DATA >1612,>C0C5,>05C3,>06A0 DATA >2406,>160B,>05C3,>06A0 DATA >23CA,>C101,>0201,>834A DATA >0460,>20CA,>06A0,>20F8 DATA >10F8,>0460,>2166,>0460 DATA >216E,>C81D,>2038,>C82D DATA >0002,>83E2,>C82D,>0004 DATA >2044,>02E0,>83E0,>C80B DATA >2040,>C020,>2044,>06A0 DATA >20DC,>C0C1,>0603,>0223 DATA >8300,>D0D3,>0983,>0603 DATA >1332,>0643,>164A,>C2A0 DATA >2038,>162D,>C0C5,>05C3 DATA >06A0,>2406,>9801,>2058 DATA >1620,>0206,>0008,>0204 DATA >834A,>C0C5,>06A0,>23CA DATA >CD01,>05C3,>0646,>15FA DATA >06A0,>22DA,>0225,>0004 DATA >C105,>C046,>06A0,>23E6 DATA >05C4,>D050,>0981,>06A0 DATA >23E6,>C2E0,>2040,>C820 DATA >203E,>830C,>02E0,>2038 DATA >0380,>0200,>0700,>C2E0 DATA >2040,>0460,>2084,>0200 DATA >1C00,>0460,>226E,>C08B DATA >0643,>16F3,>C0C5,>06A0 DATA >23CA,>C0C1,>06A0,>2406 DATA >1102,>0460,>226A,>C020 DATA >2038,>06A0,>211C,>6004 DATA >0A10,>A0C0,>06A0,>23CA DATA >0452,>06A0,>227E,>0206 DATA >834A,>CD83,>DDA0,>2058 DATA >DD84,>CD81,>C0C1,>1602 DATA >04D6,>1005,>0603,>06A0 DATA >2406,>0981,>C581,>C020 DATA >2044,>06A0,>22DA,>0460 DATA >225A,>C80B,>203A,>C805 DATA >203C,>C2E0,>601E,>069B DATA >C020,>2044,>C160,>203C DATA >D190,>0986,>C820,>830C DATA >203E,>C806,>830C,>C806 DATA >8350,>C2E0,>6012,>069B DATA >C020,>2044,>0206,>834A DATA >0204,>001C,>CD84,>DDA0 DATA >2058,>DD84,>C5A0,>831C DATA >C0A0,>830C,>1309,>C116 DATA >C0C0,>0583,>D073,>06A0 DATA >241A,>0584,>0602,>15FA DATA >C2E0,>6028,>069B,>C020 DATA >2044,>C160,>203C,>C2E0 DATA >203A,>045B,>C01D,>C06D DATA >0002,>06A0,>20DC,>C0C1 DATA >0603,>0223,>8300,>D0D3 DATA >0983,>0603,>1302,>0643 DATA >1623,>C000,>1628,>C02D DATA >0004,>C0C5,>05C3,>06A0 DATA >2406,>9801,>2058,>161D DATA >05C3,>06A0,>23CA,>C041 DATA >1307,>C181,>0601,>C0C1 DATA >06A0,>2406,>9050,>1A15 DATA >DC01,>1309,>C0C6,>0981 DATA >C141,>06A0,>2406,>DC01 DATA >0583,>0605,>15FA,>0380 DATA >06A0,>227E,>C02D,>0004 DATA >10E6,>0460,>2166,>0460 DATA >216E,>0200,>1300,>0460 DATA >2084,>06C3,>D803,>8C02 DATA >06C3,>D803,>8C02,>1000 DATA >D060,>8800,>06C1,>D060 DATA >8800,>06C1,>045B,>06C4 DATA >D804,>8C02,>06C4,>0264 DATA >4000,>D804,>8C02,>1000 DATA >D801,>8C00,>06C1,>D801 DATA >8C00,>06C1,>045B,>06C3 DATA >D803,>8C02,>06C3,>D803 DATA >8C02,>1000,>D060,>8800 DATA >045B,>06C4,>D804,>8C02 DATA >06C4,>0264,>4000,>D804 DATA >8C02,>1000,>D801,>8C00 DATA >045B,>C83E,>83E2,>02E0 DATA >83E0,>C80B,>204E,>C081 DATA >0281,>0040,>1B0A,>C0A1 DATA >6010,>0281,>0004,>1605 DATA >C0A2,>0002,>0692,>2466 DATA >1001,>0692,>02E0,>2038 DATA >C80B,>83F6,>0380,>0200 DATA >0B00,>0460,>2084,>02E0 DATA >83E0,>C80B,>204E,>06A0 DATA >000E,>02E0,>2038,>C80B DATA >83F6,>0380,>06A0,>24CA DATA >D82D,>0002,>8C00,>0380 DATA >06A0,>24CA,>D831,>8C00 DATA >0602,>16FC,>0380,>06A0 DATA >24D0,>DB60,>8800,>0002 DATA >0380,>06A0,>24D0,>DC60 DATA >8800,>0602,>16FC,>0380 DATA >C05D,>D82D,>0001,>8C02 DATA >0261,>8000,>D801,>8C02 DATA >0380,>0201,>4000,>1001 DATA >04C1,>C09D,>D820,>203D DATA >8C02,>E081,>D802,>8C02 DATA >C06D,>0002,>C0AD,>0004 DATA >045B ********************************************************** * EDITOR ASSEMBLER LOWER 8K SUPPORT * Data for Initialization of * Memory Expansion * LOW1 DATA >A55A,>2128,>2398,>225A LOW2 DATA >A000,>FFD7,>2676,>3F38 LOW3 DATA >0064,>2000,>2EAA,>2094 DATA >21C4,>2094,>2196,>2094,>21DE,>2094,>21F4 DATA >2094,>2200,>2094,>220E,>2094,>221A,>2094,>2228 DATA >209A,>22B2,>20DA,>23BA,>C80B,>2030,>D060 DATA >8349,>2060,>20FC,>132A,>C020,>8350,>1311,>06A0 DATA >2646,>101E,>0281,>3F38,>1319,>C001,>0202 DATA >834A,>8CB0,>1611,>8CB0,>160F,>8CB0,>160D,>C810 DATA >2022,>02E0,>20BA,>C020,>2022,>1309,>0690 DATA >02E0,>83E0,>C2E0,>2030,>045B,>0221,>0008,>10E4 DATA >0200,>0F00,>D800,>8322,>02E0,>83E0,>0460 DATA >00CE,>5820,>20FC,>8349,>02E0,>2094,>0380,>C83E DATA >83E2,>02E0,>83E0,>C80B,>20AA,>C081,>0281 DATA >8000,>1B07,>09C1,>0A11,>0A42,>09B2,>A0A1,>0CFA DATA >C092,>0692,>02E0,>2094,>C80B,>83F6,>0380 DATA >D060,>8373,>0981,>C87E,>8304,>F820,>20FC,>8349 DATA >02E0,>83E0,>C2E0,>2030,>045B,>02E0,>83E0 DATA >C80B,>20AA,>06A0,>000E,>02E0,>2094,>C80B,>83F6 DATA >0380,>06A0,>223A,>D82D,>0002,>8C00,>0380 DATA >06A0,>223A,>D831,>8C00,>0602,>16FC,>0380,>06A0 DATA >2240,>DB60,>8800,>0002,>0380,>06A0,>2240 DATA >DC60,>8800,>0602,>16FC,>0380,>C05D,>D82D,>0001 DATA >8C02,>0261,>8000,>D801,>8C02,>0380,>0201 DATA >4000,>1001,>04C1,>C09D,>D820,>2099,>8C02,>E081 DATA >D802,>8C02,>C06D,>0002,>C0AD,>0004,>045B DATA >0204,>834A,>C014,>C184,>04F6,>04F6,>C140,>1323 DATA >0740,>0203,>0040,>04F6,>04D6,>0280,>0064 DATA >1A13,>0280,>2710,>1A08,>0583,>C040,>04C0,>3C20 DATA >20FA,>D920,>83E3,>0003,>0583,>C040,>04C0 DATA >3C20,>20FA,>D920,>83E3,>0002,>D920,>83E1,>0001 DATA >D520,>83E7,>0545,>1101,>0514,>045B,>C17E DATA >53E0,>20FC,>C020,>8356,>C240,>0229,>FFF8,>0420 DATA >2114,>D0C1,>0983,>0704,>0202,>208C,>0580 DATA >0584,>80C4,>1306,>0420,>2114,>DC81,>9801,>20FE DATA >16F6,>C104,>1352,>0284,>0007,>154F,>04E0 DATA >83D0,>C804,>8354,>C804,>2036,>0584,>A804,>8356 DATA >C820,>8356,>2038,>02E0,>83E0,>04C1,>020C DATA >0F00,>C30C,>1301,>1E00,>022C,>0100,>04E0,>83D0 DATA >028C,>2000,>1332,>C80C,>83D0,>1D00,>0202 DATA >4000,>9812,>20FF,>16EE,>A0A0,>20A4,>1003,>C0A0 DATA >83D2,>1D00,>C092,>13E6,>C802,>83D2,>05C2 DATA >C272,>D160,>8355,>1309,>9C85,>16F2,>0985,>0206 DATA >208C,>9CB6,>16ED,>0605,>16FC,>0581,>C801 DATA >203A,>C809,>2034,>C80C,>2032,>0699,>10E2,>1E00 DATA >02E0,>209A,>C009,>0420,>2114,>09D1,>1604 DATA >0380,>02E0,>209A,>04C1,>06C1,>D741,>F3E0,>20FC DATA >0380,>C80B,>2030,>02E0,>20BA,>0420,>2124 DATA >02E0,>83E0,>1303,>C2E0,>2030,>045B,>D820,>20BA DATA >8322,>0460,>00CE,>04E0,>2022,>53E0,>20FC DATA >C020,>8356,>0420,>2120,>0008,>1332,>0220,>FFF7 DATA >0201,>0200,>0420,>210C,>0580,>C800,>202E DATA >C1E0,>2024,>C147,>04CC,>06A0,>25E0,>0283,>0001 DATA >1624,>058C,>04C3,>1023,>0283,>0046,>161E DATA >04C2,>06A0,>262E,>0283,>003A,>16F7,>C020,>202E DATA >0600,>0201,>0100,>0420,>210C,>06A0,>25E0 DATA >C020,>2022,>1307,>06A0,>2646,>1005,>CB4E,>0016 DATA >C3A0,>2022,>0380,>D740,>F3E0,>20FC,>0380 DATA >06A0,>25C2,>04C4,>D123,>2662,>0974,>C808,>202C DATA >06A0,>2594,>0464,>23F8,>0580,>0240,>FFFE DATA >C120,>2024,>A100,>1808,>8804,>2026,>1B05,>C160 DATA >2024,>C804,>2024,>100A,>C120,>2028,>A100 DATA >8804,>202A,>140C,>C160,>2028,>C804,>2028,>C1C5 DATA >0209,>0008,>06A0,>262E,>0609,>16FC,>10B6 DATA >0200,>0800,>10CC,>A005,>C800,>2022,>10AF,>A800 DATA >202C,>13AC,>0200,>0B00,>10C2,>A005,>C1C0 DATA >10A6,>A005,>DDC0,>DDE0,>20DB,>10A1,>A005,>06A0 DATA >2566,>C000,>1316,>0226,>FFF8,>8106,>1B02 DATA >0514,>1096,>8594,>16F8,>89A4,>0002,>0002,>16F4 DATA >89A4,>0004,>0004,>16F0,>C0E6,>0006,>C250 DATA >C403,>C009,>16FC,>0224,>0008,>C804,>202A,>10EA DATA >A005,>06A0,>2566,>0226,>FFF8,>8106,>13E3 DATA >C296,>1501,>050A,>8294,>16F7,>89A4,>0002,>0002 DATA >16F3,>89A4,>0004,>0004,>16EF,>C296,>1516 DATA >C0E6,>0006,>C253,>C4C0,>C0C9,>16FC,>C246,>6244 DATA >C286,>022A,>0008,>C0C6,>0643,>064A,>C693 DATA >0649,>16FB,>0224,>0008,>C804,>202A,>10D9,>CB44 DATA >0002,>0200,>0C00,>0460,>2432,>0460,>2494 DATA >C28B,>0209,>0006,>C1A0,>202A,>0226,>FFF8,>C106 DATA >8806,>2028,>1AF3,>C806,>202A,>06A0,>262E DATA >DDA0,>20E1,>0609,>16FA,>C580,>0206,>4000,>045A DATA >C28B,>04C0,>C30C,>1308,>06A0,>262E,>D020 DATA >20E1,>06A0,>262E,>A003,>045A,>0209,>0004,>06A0 DATA >262E,>06A0,>25C2,>0A40,>A003,>0609,>16F8 DATA >045A,>0223,>FFD0,>0283,>000A,>1A05,>0223,>FFF9 DATA >0283,>0019,>1B01,>045B,>0200,>0A00,>0460 DATA >2432,>02E0,>83E0,>0200,>2032,>C330,>C270,>C830 DATA >8354,>C830,>8356,>C050,>1D00,>9820,>4000 DATA >20FF,>161D,>0699,>101B,>1E00,>02E0,>20DA,>C020 DATA >202E,>0201,>20DB,>0202,>0004,>0420,>2118 DATA >7000,>0950,>1610,>0982,>C001,>0201,>203C,>0420 DATA >2118,>04C8,>0602,>11D7,>D0F1,>0983,>A203 DATA >045B,>02E0,>20DA,>04C0,>06C0,>0460,>2432,>0201 DATA >3F40,>0221,>FFF8,>C011,>1105,>8060,>202A DATA >16F9,>05CB,>045B,>0200,>0D00,>045B,>2D52,>5163 DATA >6483,>8455,>045C,>5B5F,>5EF0,>F003,>F0F0 DATA >4700,>00C8,>3F38 LOW4 DATA >5554,>4C54,>4142,>2022,>5041,>4420,>2020,>8300 DATA >4750,>4C57,>5320,>83E0,>534F,>554E,>4420 DATA >8400,>5644,>5052,>4420,>8800,>5644,>5053,>5441 DATA >8802,>5644,>5057,>4420,>8C00,>5644,>5057 DATA >4120,>8C02,>5350,>4348,>5244,>9000,>5350,>4348 DATA >5754,>9400,>4752,>4D52,>4420,>9800,>4752 DATA >4D52,>4120,>9802,>4752,>4D57,>4420,>9C00,>4752 DATA >4D57,>4120,>9C02,>5343,>414E,>2020,>000E DATA >584D,>4C4C,>4E4B,>2104,>4B53,>4341,>4E20,>2108 DATA >5653,>4257,>2020,>210C,>564D,>4257,>2020 DATA >2110,>5653,>4252,>2020,>2114,>564D,>4252,>2020 DATA >2118,>5657,>5452,>2020,>211C,>4453,>524C DATA >4E4B,>2120,>4C4F,>4144,>4552,>2124,>4750,>4C4C DATA >4E4B,>2100 *********************************************************** * * RXB Character set *********************************************************** CHARS BYTE >00,>10,>10,>10,>10,>10,>00,>10 * ! 33 BYTE >00,>50,>50,>50,>00,>00,>00,>00 * " 34 BYTE >00,>50,>50,>F8,>50,>F8,>50,>50 * # 35 BYTE >00,>20,>78,>A0,>70,>28,>F0,>20 * $ 36 BYTE >00,>C0,>C8,>10,>20,>40,>98,>18 * % 37 BYTE >00,>40,>A0,>A0,>40,>A8,>90,>68 * & 38 BYTE >00,>C0,>40,>80,>00,>00,>00,>00 * ' 39 BYTE >00,>08,>10,>20,>20,>20,>10,>08 * ( 40 BYTE >00,>10,>08,>04,>04,>04,>08,>10 * ) 41 BYTE >00,>00,>28,>10,>7C,>10,>28,>00 * * 42 BYTE >00,>00,>10,>10,>7C,>10,>10,>00 * + 43 BYTE >00,>00,>00,>00,>00,>60,>20,>40 * , 44 BYTE >00,>00,>00,>00,>F8,>00,>00,>00 * - 45 BYTE >00,>00,>00,>00,>00,>00,>60,>60 * . 46 BYTE >00,>00,>08,>10,>20,>40,>80,>00 * / 47 BYTE >00,>70,>88,>98,>A8,>C8,>88,>70 * 0 48 BYTE >00,>20,>60,>20,>20,>20,>20,>70 * 1 49 BYTE >00,>70,>88,>08,>30,>40,>80,>F8 * 2 50 BYTE >00,>70,>88,>08,>30,>08,>88,>70 * 3 51 BYTE >00,>10,>30,>50,>90,>F8,>10,>10 * 4 52 BYTE >00,>F0,>80,>80,>F0,>08,>88,>70 * 5 53 BYTE >00,>70,>80,>80,>F0,>88,>88,>70 * 6 54 BYTE >00,>F8,>08,>10,>20,>40,>40,>40 * 7 55 BYTE >00,>70,>88,>88,>70,>88,>88,>70 * 8 56 BYTE >00,>70,>88,>88,>78,>08,>88,>70 * 9 57 BYTE >00,>00,>60,>60,>00,>60,>60,>00 * : 58 BYTE >00,>00,>60,>60,>00,>60,>20,>40 * ; 59 BYTE >00,>08,>10,>20,>40,>20,>10,>08 * < 60 BYTE >00,>00,>7C,>00,>00,>7C,>00,>00 * = 61 BYTE >00,>20,>10,>08,>04,>08,>10,>20 * > 62 BYTE >00,>70,>88,>10,>20,>20,>00,>20 * ? 63 BYTE >00,>38,>44,>5C,>54,>5C,>40,>38 * @ 64 BYTE >00,>70,>88,>88,>F8,>88,>88,>88 * A 65 BYTE >00,>F0,>48,>48,>70,>48,>48,>F0 * B 66 BYTE >00,>70,>88,>80,>80,>80,>88,>70 * C 67 BYTE >00,>F0,>48,>48,>48,>48,>48,>F0 * D 68 BYTE >00,>F8,>80,>80,>F0,>80,>80,>F8 * E 69 BYTE >00,>F8,>80,>80,>F0,>80,>80,>80 * F 70 BYTE >00,>70,>88,>80,>80,>98,>88,>78 * G 71 BYTE >00,>88,>88,>88,>F8,>88,>88,>88 * H 72 BYTE >00,>F8,>20,>20,>20,>20,>20,>F8 * I 73 BYTE >00,>08,>08,>08,>08,>08,>88,>70 * J 74 BYTE >00,>88,>90,>A0,>C0,>A0,>90,>88 * K 75 BYTE >00,>80,>80,>80,>80,>80,>80,>F8 * L 76 BYTE >00,>88,>D8,>A8,>A8,>88,>88,>88 * M 77 BYTE >00,>88,>88,>C8,>A8,>98,>88,>88 * N 78 BYTE >00,>70,>88,>88,>88,>88,>88,>70 * O 79 BYTE >00,>F0,>88,>88,>88,>F0,>80,>80 * P 80 BYTE >00,>70,>88,>88,>88,>A8,>90,>68 * Q 81 BYTE >00,>F0,>88,>88,>F0,>A0,>90,>88 * R 82 BYTE >00,>70,>88,>80,>70,>08,>88,>70 * S 83 BYTE >00,>F8,>20,>20,>20,>20,>20,>20 * T 84 BYTE >00,>44,>44,>44,>44,>44,>44,>38 * U 85 BYTE >00,>44,>44,>44,>28,>28,>10,>10 * V 86 BYTE >00,>88,>88,>88,>88,>A8,>A8,>50 * W 87 BYTE >00,>88,>88,>50,>20,>50,>88,>88 * X 88 BYTE >00,>88,>88,>88,>50,>20,>20,>20 * Y 89 BYTE >00,>F8,>08,>10,>20,>40,>80,>F8 * Z 90 BYTE >00,>78,>40,>40,>40,>40,>40,>78 * [ 91 BYTE >00,>00,>80,>40,>20,>10,>08,>00 * \ 92 BYTE >00,>F0,>10,>10,>10,>10,>10,>F0 * ] 93 BYTE >00,>20,>50,>88,>00,>00,>00,>00 * ^ 94 BYTE >00,>00,>00,>00,>00,>00,>00,>FF * _ 95 BYTE >00,>18,>10,>08,>00,>00,>00,>00 * ` 96 BYTE >00,>00,>00,>60,>10,>70,>90,>68 * a 97 BYTE >00,>00,>40,>40,>70,>48,>48,>B0 * b 98 BYTE >00,>00,>00,>60,>90,>80,>90,>60 * c 99 BYTE >00,>00,>10,>10,>70,>90,>90,>68 * d 100 BYTE >00,>00,>00,>60,>90,>E0,>80,>70 * e 101 BYTE >00,>00,>30,>40,>E0,>40,>40,>40 * f 102 BYTE >00,>00,>00,>70,>90,>70,>10,>60 * g 103 BYTE >00,>00,>80,>80,>E0,>90,>90,>90 * h 104 BYTE >00,>00,>20,>00,>20,>20,>20,>70 * i 105 BYTE >00,>00,>10,>10,>10,>10,>90,>60 * j 106 BYTE >00,>00,>80,>90,>A0,>C0,>A0,>90 * k 107 BYTE >00,>00,>60,>20,>20,>20,>20,>70 * l 108 BYTE >00,>00,>00,>D0,>A8,>A8,>A8,>A8 * m 109 BYTE >00,>00,>00,>B0,>48,>48,>48,>48 * n 110 BYTE >00,>00,>00,>60,>90,>90,>90,>60 * o 111 BYTE >00,>00,>F0,>48,>48,>70,>40,>40 * p 112 BYTE >00,>00,>78,>90,>90,>70,>10,>10 * q 113 BYTE >00,>00,>00,>B0,>C8,>80,>80,>80 * r 114 BYTE >00,>00,>00,>70,>80,>70,>08,>F0 * s 115 BYTE >00,>00,>40,>E0,>40,>40,>50,>20 * t 116 BYTE >00,>00,>00,>90,>90,>90,>90,>68 * u 117 BYTE >00,>00,>00,>88,>88,>88,>50,>20 * v 118 BYTE >00,>00,>00,>88,>88,>A8,>A8,>50 * w 119 BYTE >00,>00,>00,>88,>50,>20,>50,>88 * x 120 BYTE >00,>00,>00,>48,>48,>38,>08,>70 * y 121 BYTE >00,>00,>00,>F8,>10,>20,>40,>F8 * z 122 BYTE >00,>18,>20,>20,>40,>20,>20,>18 * { 123 BYTE >00,>20,>20,>20,>00,>20,>20,>20 * | 124 BYTE >00,>C0,>20,>20,>10,>20,>20,>C0 * } 125 BYTE >00,>00,>00,>40,>A8,>10,>00,>00 * ~ 126 *********************************************************** END 1 Quote Link to comment Share on other sites More sharing options...
+Lee Stewart Posted June 11, 2021 Share Posted June 11, 2021 1 hour ago, RXB said: Ok have the ROM3 set up and looks great, still have to write the GPL to make it work. I will take a closer look at your routines later. For now, a couple of comments: Your DROLL routine’s return should be B *R8 * RETURN Your MIT routine does not need to save the R11 return because it does not contain any BL instructions that would trash it: MIT MOVB @>83E7,*R15 * Write out read address MOVB R3,*R15 MOVB @>8800,R7 * Read a byte MOVB @>83EB,*R15 * Write out write address ORI R5,>4000 * Enable VDP write MOVB R5,*R15 MOVB R7,@>8C00 * Write the byte RT * RETURN ...lee 2 1 Quote Link to comment Share on other sites More sharing options...
+Lee Stewart Posted June 12, 2021 Share Posted June 12, 2021 On 6/10/2021 at 8:25 AM, Lee Stewart said: I have not had time to test it. I have tested my routines. Up and down rolls work as expected. I have work to do on the left and right rolls—I obviously made some wrong row and column calculations. I will have them fixed later tonight or early tomorrow. ...lee 1 Quote Link to comment Share on other sites More sharing options...
RXB Posted June 12, 2021 Share Posted June 12, 2021 I am writing my GPL routines now, including SCROLL up, left, right and down too. Along with ROLL up, left, right and down. 2 Quote Link to comment Share on other sites More sharing options...
+Lee Stewart Posted June 13, 2021 Share Posted June 13, 2021 (edited) On 6/11/2021 at 8:45 PM, Lee Stewart said: I have tested my routines. Up and down rolls work as expected. I have work to do on the left and right rolls—I obviously made some wrong row and column calculations. I will have them fixed later tonight or early tomorrow. ...lee Actually, all my code was fine except for one small problem. I was reusing R0 from one row to the next, while forgetting that writing the VDP write address would change it by ORing >4000 every time. All I needed to do was compensate for that by stripping that change with ANDI R0,>3FFF just before returning from writing the VDP write/read address. The corrected code is in the spoiler: Spoiler **************************************************************** AORG >6000 TITL 'RXB ROM3' GR0LB EQU >83E1 * GPLWS R0 LSB FAC EQU >834A * RAM line buffer SAVRTN EQU >836C * free space after RAM line buffer VBUFF EQU >03C0 * line buffer in VRAM VDPRD EQU >8800 * VDP Read Data address VDPWD EQU >8C00 * VDP Write Data address * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Write VRAM address * Expects address in R0 * * BL here for writing data * VWADDW ORI R0,>4000 * set to write VRAM data * * BL here for reading data * VWADD MOVB @GR0LB,*R15 * write LSB of R0 to VDPWA MOVB R0,*R15 * write MSB of R0 to VDPWA ANDI R0,>3FFF * ensure R0 returned intact RT * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * The following utilities expect * R0 = VRAM address * R1 = RAM result for 1 byte or RAM address for multiple bytes * R2 = count for multi-byte copies * * R10 will be destroyed * * Copy one byte from VRAM (R0) to R1 * VSR MOV R11,R10 * save return BL @VWADD * write out VRAM read address MOVB @VDPRD,R1 * read VRAM byte B *R10 * return to caller * * Copy one byte from R1 to VRAM (R0) * VSW MOV R11,R10 * save return BL @VWADDW * write out VRAM write address MOVB R1,@VDPWD * write VRAM byte B *R10 * return to caller * * Copy R2 bytes from VRAM (R0) to RAM (R1) * VMR MOV R11,R10 * save return BL @VWADD * write out VRAM read address VMRLP MOVB @VDPRD,*R1+ * read next VRAM byte to RAM DEC R2 * dec count JNE VMRLP * repeat if not done B *R10 * return to caller * * Copy R2 bytes from RAM (R1) to VRAM (R0) * VMW MOV R11,R10 * save return BL @VWADDW * write out VRAM write address VMWLP MOVB *R1+,@VDPWD * write next VRAM byte from RAM DEC R2 * dec count JNE VMWLP * repeat if not done B *R10 * return to caller * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * RROLL * RROLL MOV R11,@SAVRTN * save return address CLR R0 * set to screen start LI R3,24 * rows to roll * Write row to RAM buffer RROLLP LI R1,FAC * set RAM buffer LI R2,32 * count BL @VMR * copy row to RAM buffer * copy last column to first MOVB @FAC+31,R1 * get RAM byte to copy BL @VSW * write end byte to row start * copy 1st 31 columns one column right INC R0 * start at 2nd column LI R1,FAC * reset RAM buffer pointer LI R2,31 * count BL @VMW * copy rest of line * Process next row AI R0,31 * next row DEC R3 * dec row count JNE RROLLP * roll next row if not done MOV @SAVRTN,R11 * restore return address RT * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * LROLL * LROLL MOV R11,@SAVRTN * save return address CLR R0 * set to screen start LI R3,24 * rows to roll * Write row to RAM buffer LROLLP LI R1,FAC * set RAM buffer LI R2,32 * count BL @VMR * copy row to RAM buffer * copy 1st 31 columns one column left LI R1,FAC+1 * set RAM buffer pointer to 2nd char LI R2,31 * count BL @VMW * copy rest of line * copy first column to last AI R0,31 * set VRAM dest to last column MOVB @FAC,R1 * get RAM byte to copy BL @VSW * write start byte to row end * Process next row INC R0 * next row DEC R3 * dec row count JNE LROLLP * roll next row if not done MOV @SAVRTN,R11 * restore return address RT * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * UROLL * UROLL MOV R11,@SAVRTN * save return address CLR R0 * set to screen start LI R3,23 * rows to roll (all but 1st) * Write first row to RAM buffer LI R1,FAC * set RAM buffer LI R2,32 * count BL @VMR * copy row to RAM buffer * Copy RAM buffer to VRAM buffer LI R0,VBUFF * set VRAM dest to VBUFF LI R1,FAC * set RAM buffer LI R2,32 * count BL @VMW * copy row to VBUFF (VRAM buffer) * Start copy loop at 2nd row LI R0,32 * point to 2nd row * Write row to RAM buffer UROLLP LI R1,FAC * set RAM buffer LI R2,32 * count BL @VMR * copy row to RAM buffer * Copy to previous row AI R0,-32 * back up 1 row LI R1,FAC * reset RAM buffer pointer LI R2,32 * count BL @VMW * copy to previous row * Process next row AI R0,64 * next row DEC R3 * dec row count JNE UROLLP * roll next row if not done * Copy saved row to RAM LI R0,VBUFF * set VRAM source LI R1,FAC * set RAM buffer LI R2,32 * count BL @VMR * copy row to RAM buffer * Copy saved row to last row LI R0,736 * point to last row LI R1,FAC * reset RAM buffer pointer LI R2,32 * count BL @VMW * copy to last row MOV @SAVRTN,R11 * restore return address RT * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * DROLL * DROLL MOV R11,@SAVRTN * save return address LI R0,736 * set to last row LI R3,23 * rows to roll (all but last) * Write last row to RAM buffer LI R1,FAC * set RAM buffer LI R2,32 * count BL @VMR * copy row to RAM buffer * Copy RAM buffer to VRAM buffer LI R0,VBUFF * set VRAM dest to VBUFF LI R1,FAC * set RAM buffer LI R2,32 * count BL @VMW * copy row to VBUFF (VRAM buffer) * Start copy loop at 2nd-to-last row LI R0,704 * point to row 22 * Write row to RAM buffer DROLLP LI R1,FAC * set RAM buffer LI R2,32 * count BL @VMR * copy row to RAM buffer * Copy to next row AI R0,32 * down 1 row LI R1,FAC * reset RAM buffer pointer LI R2,32 * count BL @VMW * copy to next row * Process next row AI R0,-64 * back up 2 rows DEC R3 * dec row count JNE DROLLP * roll next row if not done * Copy saved row to RAM LI R0,VBUFF * set VRAM source LI R1,FAC * set RAM buffer LI R2,32 * count BL @VMR * copy row to RAM buffer * Copy saved row to first row CLR R0 * point to first row LI R1,FAC * reset RAM buffer pointer LI R2,32 * count BL @VMW * copy to first row MOV @SAVRTN,R11 * restore return address RT END Now, I need to compare my code to Rich’s for speed. ...lee Edited June 14, 2021 by Lee Stewart Redid AORG for RXB 5 Quote Link to comment Share on other sites More sharing options...
oddemann Posted June 13, 2021 Share Posted June 13, 2021 Inspiring to see how you push yourself and one another to make a better program! Programming/Coding makes for better people :p hehehehe 2 Quote Link to comment Share on other sites More sharing options...
+Lee Stewart Posted June 13, 2021 Share Posted June 13, 2021 On 6/11/2021 at 1:41 PM, RXB said: Ok have the ROM3 set up and looks great, still have to write the GPL to make it work. Actually, your code does not work for Right and Down scrolling because you are copying overlapping code in the wrong direction, i.e., each copy destroys the source for the next copy. There were a couple of other errors, as well. You also had a couple of redundant routines. I fixed all of that in the spoiler below: Spoiler **************************************************************** AORG >6000 TITL 'RXB ROM3' ************************************************************ * CALL RROLL(direction,repetion,...) * ************************************************************ RROLL MOV R11,R8 * save return address LI R3,31 * 31 right edge Screen Address BL @C2BCPY * Move IT * Buffer has 24 far right characters CLR R3 * Screen address LI R5,1 * Destination * Copy everything on screen 1 char right. Doesn't matter that * first column will get wrong chars because they will be * overwritten by previous last column in next section. LI R1,767 * copy all but last char on screen BL @H2LCPY * Move IT, high to low VRAM * Moved all on screen 1 right CLR R5 * 0 left edge Screen Address BL @B2CCPY * Move IT B *R8 * RETURN ************************************************************ * CALL LROLL(direction,repetion,...) * ************************************************************ LROLL MOV R11,R8 * save return address CLR R3 * 0 left edge Screen Address BL @C2BCPY * Move IT * Buffer has 24 far left characters LI R3,1 * Screen address CLR R5 * Destination * Copy everything on screen 1 char left. Doesn't matter that * last column will get wrong chars because they will be * overwritten by previous first column in next section. LI R1,767 * copy all but first char on screen BL @L2HCPY * Move IT, low to high VRAM * Moved all on screen 1 left LI R5,31 * 31 right edge Screen Address BL @B2CCPY * Move IT B *R8 * RETURN *********************************************************** * CALL UROLL(direction,repetion,...) * ************************************ *********************** UROLL MOV R11,R8 * save return address CLR R3 * 0 top Sreeen Adress LI R5,>03C0 * Buffer for 32 characters LI R1,32 * 32 bytes length BL @L2HCPY * Move IT * Buffer has 32 top line characters LI R3,32 * 2nd line Screen address CLR R5 * 0 screen Destination LI R1,736 * Number of Bytes BL @L2HCPY * Move IT * Moved all on screen up 1 LI R3,>03C0 * Buffer for 32 characters LI R5,736 * Bottom left edge Screen Address LI R1,32 * Get 32 Bytes length BL @L2HCPY * Move IT B *R8 * RETURN * ********************************************************** * CALL DROLL(direction,repetion,...) * ************************************************************ DROLL MOV R11,R8 * save return address LI R3,736 * Bottom of Sreeen Adress LI R5,>03C0 * Buffer for 32 characters LI R1,32 * 32 bytes length BL @L2HCPY * Move IT, low to high VRAM * Buffer has 32 top line characters CLR R3 * 0 Screen address LI R5,32 * 2nd line Destination LI R1,736 * Number of Bytes BL @H2LCPY * Move IT, high to low VRAM * Moved all on screen down 1 LI R3,>03C0 * Buffer for 32 characters CLR R5 * Top left edge Screen Address LI R1,32 * Get 32 Bytes BL @L2HCPY * Move IT, low to high VRAM B *R8 * RETURN *********************************************************** ***Low VRAM to High VRAM Copy****************************** *********************************************************** L2HCPY MOV R11,R9 * save return address L2HCPR BL @MIT * Move IT INC R3 * source+1 INC R5 * dest+1 DEC R1 * COUNTER-1 JNE L2HCPR * 0? No, loop B *R9 * RETURN *********************************************************** ***High VRAM to Low VRAM Copy****************************** *********************************************************** H2LCPY MOV R11,R9 * save return address * Adjust source and dest to copy from last byte to first A R1,R3 * one past end of source DEC R3 * adjust to last source char A R1,R5 * one past end of dest DEC R5 * adjust to last dest char H2LCPR BL @MIT * Move IT DEC R3 * source-1 DEC R5 * dest-1 DEC R1 * counter-1 JNE H2LCPR * 0? No, loop B *R9 * RETURN ************************************************************ ***Column Copy to VRAM Buffer******************************* ************************************************************ C2BCPY MOV R11,R9 * save return address LI R2,24 * ROW counter LI R5,>03C0 * column buffer C2BCPR BL @MIT * Move IT INC R5 * Buffer+1 AI R3,32 * Screen Address+32 DEC R2 * ROW COUNTER-1 JNE C2BCPR * 0? No, loop B *R9 * RETURN ************************************************************ ***VRAM Buffer to Column Copy******************************* ************************************************************ B2CCPY MOV R11,R9 * save return address LI R2,24 * ROW counter LI R3,>03C0 * column buffer B2CCPR BL @MIT * Move IT INC R3 * Buffer+1 AI R5,32 * Screen Address+32 DEC R2 * ROW COUNTER-1 JNE B2CCPR * 0? No, loop B *R9 * RETURN ************************************************************ ***VRAM to VRAM Single Byte Copy**************************** ************************************************************ MIT MOVB @>83E7,*R15 * Write out read address MOVB R3,*R15 MOVB @>8800,R7 * Read a byte MOVB @>83EB,*R15 * Write out write address ORI R5,>4000 * Enable VDP write MOVB R5,*R15 MOVB R7,@>8C00 * Write the byte RT * RETURN END ...lee 3 1 Quote Link to comment Share on other sites More sharing options...
+Lee Stewart Posted June 14, 2021 Share Posted June 14, 2021 (edited) On 6/12/2021 at 10:14 PM, Lee Stewart said: Now, I need to compare my code to Rich’s for speed. OK—here is the comparison of my rolling routines (LESROLL, see post #1234) with Rich’s (@RXB's) corrected rolling routines (RXBROLL, see post #1236)— LESROLL— UP (500 rows)..........22 seconds DOWN (500 rows)........21 seconds RIGHT (500 columns)....22 seconds LEFT (500 columns).....21 seconds RXBROLL— UP (500 rows)..........47 seconds DOWN (500 rows)........46 seconds RIGHT (500 columns)....48 seconds LEFT (500 columns).....48 seconds Rich’s routines take a hair more than twice as long as mine. The reason for this is that every byte that RXBROLL moves involves 2 VDP address writes, whereas, LESROLL moves 32 bytes for each row to RAM and back using 2 VDP address writes for vertical rolls; 32 bytes for each row to RAM and back using 3 VDP address writes for horizontal rolls. Here are the number of VDP address writes used to roll 1 column or 1 row: LESROLL— UP.......50 DOWN.....50 RIGHT....72 LEFT.....72 RXBROLL— UP.....1600 DOWN...1600 RIGHT..1630 LEFT...1630 The RXBROLL code is pretty tight at 280 bytes. I could probably tighten up LESROLL a bit from its 422 bytes, but surely not to 280 bytes. The efficiency costs a little room. ...lee Edited June 17, 2021 by Lee Stewart CORRECTION of Number of Rolls in Test 2 1 Quote Link to comment Share on other sites More sharing options...
RXB Posted June 14, 2021 Share Posted June 14, 2021 Will have to work on it tomorrow and love your changes, so far not a issue for size just used to making code as compact as possible. 1 Quote Link to comment Share on other sites More sharing options...
+Lee Stewart Posted June 14, 2021 Share Posted June 14, 2021 (edited) In post #1234, I forgot to change the AORG directive to what Rich (@RXB) was using. I corrected it in the previous post and here it is again, just in case: Spoiler ************************************************************ AORG >6000 TITL 'RXB ROM3' UNUSED DATA >0000,>0000,>0000,>0000 DATA >0000,>0000,>0000,>0000 ************************************************************ * XML table number 7 for RXB ROM3 - must have * * it's origin at >6010 * ************************************************************ * 0 1 2 3 4 5 6 DATA RROLL,LROLL,UROLL,DROLL,>0000,>0000,>0000 * 7 8 9 A B C D DATA >0000,>0000,>0000,>0000,>0000,>0000,>0000 * E F DATA >0000,>0000 ************************************************************ * XML table number 8 for RXB ROM3 - must have * * it's origin at >6030 * ************************************************************ * 0 1 2 3 4 5 6 7 DATA >0000,>0000,>0000,>0000,>0000,>0000,>0000,>0000 * 8 9 A B C D E F DATA >0000,>0000,>0000,>0000,>0000,>0000,>0000,>0000 GR0LB EQU >83E1 * GPLWS R0 LSB FAC EQU >834A * RAM line buffer SAVRTN EQU >836C * free space after RAM line buffer VBUFF EQU >03C0 * line buffer in VRAM VDPRD EQU >8800 * VDP Read Data address VDPWD EQU >8C00 * VDP Write Data address * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Write VRAM address * Expects address in R0 * * BL here for writing data * VWADDW ORI R0,>4000 * set to write VRAM data * * BL here for reading data * VWADD MOVB @GR0LB,*R15 * write LSB of R0 to VDPWA MOVB R0,*R15 * write MSB of R0 to VDPWA ANDI R0,>3FFF * ensure R0 returned intact RT * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * The following utilities expect * R0 = VRAM address * R1 = RAM result for 1 byte or RAM address for multiple bytes * R2 = count for multi-byte copies * * R10 will be destroyed * * Copy one byte from VRAM (R0) to R1 * VSR MOV R11,R10 * save return BL @VWADD * write out VRAM read address MOVB @VDPRD,R1 * read VRAM byte B *R10 * return to caller * * Copy one byte from R1 to VRAM (R0) * VSW MOV R11,R10 * save return BL @VWADDW * write out VRAM write address MOVB R1,@VDPWD * write VRAM byte B *R10 * return to caller * * Copy R2 bytes from VRAM (R0) to RAM (R1) * VMR MOV R11,R10 * save return BL @VWADD * write out VRAM read address VMRLP MOVB @VDPRD,*R1+ * read next VRAM byte to RAM DEC R2 * dec count JNE VMRLP * repeat if not done B *R10 * return to caller * * Copy R2 bytes from RAM (R1) to VRAM (R0) * VMW MOV R11,R10 * save return BL @VWADDW * write out VRAM write address VMWLP MOVB *R1+,@VDPWD * write next VRAM byte from RAM DEC R2 * dec count JNE VMWLP * repeat if not done B *R10 * return to caller * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * RROLL * RROLL MOV R11,@SAVRTN * save return address CLR R0 * set to screen start LI R3,24 * rows to roll * Write row to RAM buffer RROLLP LI R1,FAC * set RAM buffer LI R2,32 * count BL @VMR * copy row to RAM buffer * copy last column to first MOVB @FAC+31,R1 * get RAM byte to copy BL @VSW * write end byte to row start * copy 1st 31 columns one column right INC R0 * start at 2nd column LI R1,FAC * reset RAM buffer pointer LI R2,31 * count BL @VMW * copy rest of line * Process next row AI R0,31 * next row DEC R3 * dec row count JNE RROLLP * roll next row if not done MOV @SAVRTN,R11 * restore return address RT * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * LROLL * LROLL MOV R11,@SAVRTN * save return address CLR R0 * set to screen start LI R3,24 * rows to roll * Write row to RAM buffer LROLLP LI R1,FAC * set RAM buffer LI R2,32 * count BL @VMR * copy row to RAM buffer * copy 1st 31 columns one column left LI R1,FAC+1 * set RAM buffer pointer to 2nd char LI R2,31 * count BL @VMW * copy rest of line * copy first column to last AI R0,31 * set VRAM dest to last column MOVB @FAC,R1 * get RAM byte to copy BL @VSW * write start byte to row end * Process next row INC R0 * next row DEC R3 * dec row count JNE LROLLP * roll next row if not done MOV @SAVRTN,R11 * restore return address RT * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * UROLL * UROLL MOV R11,@SAVRTN * save return address CLR R0 * set to screen start LI R3,23 * rows to roll (all but 1st) * Write first row to RAM buffer LI R1,FAC * set RAM buffer LI R2,32 * count BL @VMR * copy row to RAM buffer * Copy RAM buffer to VRAM buffer LI R0,VBUFF * set VRAM dest to VBUFF LI R1,FAC * set RAM buffer LI R2,32 * count BL @VMW * copy row to VBUFF (VRAM buffer) * Start copy loop at 2nd row LI R0,32 * point to 2nd row * Write row to RAM buffer UROLLP LI R1,FAC * set RAM buffer LI R2,32 * count BL @VMR * copy row to RAM buffer * Copy to previous row AI R0,-32 * back up 1 row LI R1,FAC * reset RAM buffer pointer LI R2,32 * count BL @VMW * copy to previous row * Process next row AI R0,64 * next row DEC R3 * dec row count JNE UROLLP * roll next row if not done * Copy saved row to RAM LI R0,VBUFF * set VRAM source LI R1,FAC * set RAM buffer LI R2,32 * count BL @VMR * copy row to RAM buffer * Copy saved row to last row LI R0,736 * point to last row LI R1,FAC * reset RAM buffer pointer LI R2,32 * count BL @VMW * copy to last row MOV @SAVRTN,R11 * restore return address RT * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * DROLL * DROLL MOV R11,@SAVRTN * save return address LI R0,736 * set to last row LI R3,23 * rows to roll (all but last) * Write last row to RAM buffer LI R1,FAC * set RAM buffer LI R2,32 * count BL @VMR * copy row to RAM buffer * Copy RAM buffer to VRAM buffer LI R0,VBUFF * set VRAM dest to VBUFF LI R1,FAC * set RAM buffer LI R2,32 * count BL @VMW * copy row to VBUFF (VRAM buffer) * Start copy loop at 2nd-to-last row LI R0,704 * point to row 22 * Write row to RAM buffer DROLLP LI R1,FAC * set RAM buffer LI R2,32 * count BL @VMR * copy row to RAM buffer * Copy to next row AI R0,32 * down 1 row LI R1,FAC * reset RAM buffer pointer LI R2,32 * count BL @VMW * copy to next row * Process next row AI R0,-64 * back up 2 rows DEC R3 * dec row count JNE DROLLP * roll next row if not done * Copy saved row to RAM LI R0,VBUFF * set VRAM source LI R1,FAC * set RAM buffer LI R2,32 * count BL @VMR * copy row to RAM buffer * Copy saved row to first row CLR R0 * point to first row LI R1,FAC * reset RAM buffer pointer LI R2,32 * count BL @VMW * copy to first row MOV @SAVRTN,R11 * restore return address RT END ...lee Edited June 17, 2021 by Lee Stewart Corrected Code Header to Rich’s Code 1 1 Quote Link to comment Share on other sites More sharing options...
RXB Posted June 14, 2021 Share Posted June 14, 2021 LEE going to use your suggestion to save 32 bytes of the rolled line off screen to FAC as suggested instead of using VDP Rollout area >03C0. As I save the REPETITON value in SREF (>831C) used for only making new strings or moving strings in XB. So this should speed up ROLL over all speed slightly. When I get to making RXB HPUT and VPUT commands into Assembly ROMs this will also speed up SCROLLs. 2 Quote Link to comment Share on other sites More sharing options...
+TheBF Posted June 15, 2021 Share Posted June 15, 2021 This sounds like a revolution in interpreted X BASIC. Nice team work. 1 1 Quote Link to comment Share on other sites More sharing options...
RXB Posted June 15, 2021 Share Posted June 15, 2021 Did a mod to use FAC as buffer and not used VDP to save VDP. What do you think? ************************************************************ AORG >6000 TITL 'RXB ROM3' UNUSED DATA >0000,>0000,>0000,>0000 DATA >0000,>0000,>0000,>0000 ************************************************************ * XML table number 7 for RXB ROM3 - must have * * it's origin at >6010 * ************************************************************ * 0 1 2 3 4 5 6 DATA RROLL,LROLL,UROLL,DROLL,>0000,>0000,>0000 * 7 8 9 A B C D DATA >0000,>0000,>0000,>0000,>0000,>0000,>0000 * E F DATA >0000,>0000 ************************************************************ * XML table number 8 for RXB ROM3 - must have * * it's origin at >6030 * ************************************************************ * 0 1 2 3 4 5 6 7 DATA >0000,>0000,>0000,>0000,>0000,>0000,>0000,>0000 * 8 9 A B C D E F DATA >0000,>0000,>0000,>0000,>0000,>0000,>0000,>0000 ************************************************************ * Start of routines * ************************************************************ * Windy XB routines from previous Assembly adapted ************************************************************ * repetition = repeat number times ************************************************************ ************************************************************ * CALL RROLL(repetion,...) * ************************************************************ RROLL MOV R11,R8 * save return address LI R3,31 * 31 right edge Screen Address BL @VGWITE * Move IT (VDP to FAC RAM) * Buffer has 24 far right characters CLR R3 * Screen address LI R5,1 * Destination * Copy everything on screen 1 char right. Doesn't matter that * first column will get wrong chars because they will be * overwritten by previous last column in next section. LI R1,767 * copy all but last char on screen BL @H2LCPY * Move IT, high to low VRAM * Moved all on screen 1 right CLR R3 * 0 left edge Screen Address LI R2,24 * ROW counter BL @B2CCPY * Move IT B *R8 * RETURN ************************************************************ * CALL LROLL(repetion,...) * ************************************************************ LROLL MOV R11,R8 * save return address CLR R3 * 0 left edge Screen Address BL @C2BCPY * Move IT * Buffer has 24 far left characters LI R3,1 * Screen address CLR R5 * Destination * Copy everything on screen 1 char left. Doesn't matter that * last column will get wrong chars because they will be * overwritten by previous first column in next section. LI R1,767 * copy all but first char on screen BL @L2HCPY * Move IT, low to high VRAM * Moved all on screen 1 left LI R3,31 * 31 right edge Screen Address BL @B2CCPY * Move IT B *R8 * RETURN *********************************************************** * CALL UROLL(repetion,...) * *********************************************************** UROLL MOV R11,R8 * save return address CLR R3 * 0 top Sreeen Adress LI R2,32 * 32 bytes length BL @L2HCPY * Move IT * Buffer has 32 top line characters LI R3,32 * 2nd line Screen address CLR R5 * 0 screen Destination LI R1,736 * Number of Bytes BL @L2HCPY * Move IT * Moved all on screen up 1 LI R3,736 * Bottom left edge Screen Address LI R2,32 * Get 32 Bytes length BL @L2HCPY * Move IT B *R8 * RETURN * ********************************************************** * CALL DROLL(repetion,...) * ************************************************************ DROLL MOV R11,R8 * save return address LI R3,736 * Bottom of Sreeen Adress LI R2,32 * 32 bytes length BL @L2HCPY * Move IT, low to high VRAM * Buffer has 32 top line characters CLR R3 * 0 Screen address LI R5,32 * 2nd line Destination LI R1,736 * Number of Bytes BL @H2LCPY * Move IT, high to low VRAM * Moved all on screen down 1 CLR R3 * Top of screen LI R2,32 * Get 32 Bytes BL @L2HCPY * Move IT, low to high VRAM B *R8 * RETURN *********************************************************** ** Low RAM to High VDP Copy ******************************* *********************************************************** L2HCPY MOV R11,R9 * save return address LI R5,FAC * FAC RAM BUFFER L2HCPR BL @GVWITE * Move IT (RAM to VDP) AI R3,32 * Screen Address+1 INC R5 * Buffer+1 DEC R2 * COUNTER-1 JNE L2HCPR * 0? No, loop B *R9 * RETURN *********************************************************** ** High VDP to Low VDP Copy ******************************* *********************************************************** H2LCPY MOV R11,R9 * save return address * Adjust source and dest to copy from last byte to first A R1,R3 * one past end of source DEC R3 * adjust to last source char A R1,R5 * one past end of dest DEC R5 * adjust to last dest char H2LCPR BL @MVDN * Move IT DEC R3 * source-1 DEC R5 * dest-1 DEC R1 * counter-1 JNE H2LCPR * 0? No, loop B *R9 * RETURN ************************************************************ ** Column Copy VDP to RAM FAC Buffer *********************** ************************************************************ C2BCPY MOV R11,R9 * save return address LI R2,24 * ROW counter LI R5,FAC * FAC RAM BUFFER C2BCPR BL @VGWITE * Move IT (VDP to RAM) DEC R2 * ROW COUNTER-1 JNE C2BCPR * 0? No, loop B *R9 * RETURN ************************************************************ ** RAM Buffer to Column Copy ****************************** ************************************************************ B2CCPY MOV R11,R9 * save return address LI R2,24 * ROW counter LI R5,FAC * FAC RAM BUFFER B2CCPR BL @GVWITE * Move IT (RAM to VDP) DEC R2 * ROW COUNTER-1 JNE B2CCPR * 0? No, loop B *R9 * RETURN ************************************************************ ** VRAM to VRAM Single Byte Copy *************************** ************************************************************ MVDN MOVB @>83E7,*R15 * R3LSB Write out read address MOVB R3,*R15 * R3MSB Write out read address MOVB @>8800,R7 * Read VDP data byte MOVB @>83EB,*R15 * R5LSB Write out write address ORI R5,>4000 * Enable VDP write MOVB R5,*R15 * R5MSB Write out write address MOVB R7,@>8C00 * Write vdp data byte RT * RETURN ************************************************************ ** VDP to RAM Single Byte Copy ***************************** ************************************************************ VGWITE MOVB @>83E7,*R15 * R3LSB Write out read address ORI R2,>4000 * Enable VDP write MOVB R3,*R15 * R3MSB Write out read address NOP MOVB @>8800,*R5+ * Read VDP data byte to FAC INC R5 * Buffer+1 AI R3,32 * Screen Address+32 RT ************************************************************ ** RAM to VDP Single Byte Copy ***************************** ************************************************************ GVWITE MOVB @>83E7,*R15 * Write out read address ORI R3,>4000 * Enable VDP write MOVB R3,*R15 * R3MSB Write out read address MOVB *R5+,@>8C00 * Move byte FAC RAM to VDP ADDRESS INC R5 * Buffer+1 AI R3,32 * Screen Address+32 RT *********************************************************** * >7000 data routines * ALCEND is EA INIT * LOW1 is XB INIT * CHARS is RXB character set definitions 8 bytes each *********************************************************** AORG >7000 *********************************************************** ALCEND DATA >205A,>24F4,>4000,>AA55 DATA >2038,>2096,>2038,>217E DATA >2038,>21E2,>2038,>234C DATA >2038,>2432,>2038,>246E DATA >2038,>2484,>2038,>2490 DATA >2038,>249E,>2038,>24AA DATA >2038,>24B8,>2038,>2090 DATA >0000,>0000,>0000,>0000 DATA >0000,>0000,>0000,>0000 DATA >0000,>0000,>0000,>0000 DATA >0000,>0000,>0000,>0000 DATA >6520,>C060,>2004,>0281 DATA >4000,>130E,>C001,>0202 DATA >834A,>8CB0,>1606,>8CB0 DATA >1604,>8CB0,>1602,>C030 DATA >0450,>0221,>0008,>10EF DATA >0200,>2500,>C800,>8322 DATA >02E0,>83E0,>0460,>00CE DATA >C81D,>8322,>10F9,>C01D DATA >C06D,>0002,>06A0,>20DC DATA >C0C1,>0603,>0223,>8300 DATA >D0D3,>1361,>0983,>0643 DATA >1612,>C000,>165C,>C0C5 DATA >05C3,>06A0,>2406,>1653 DATA >05C3,>06A0,>23CA,>0204 DATA >834A,>0202,>0008,>DC74 DATA >0602,>15FD,>0380,>06A0 DATA >20F8,>10F5,>C041,>1347 DATA >0A81,>9060,>8312,>1143 DATA >0981,>C141,>0A35,>0225 DATA >0008,>A160,>8310,>045B DATA >C24B,>0643,>1634,>C0C5 DATA >06A0,>23CA,>C0C1,>06A0 DATA >2406,>112D,>06A0,>211C DATA >06A0,>23CA,>6004,>0A30 DATA >A040,>0459,>C28B,>0A51 DATA >09D1,>C201,>D120,>8343 DATA >0984,>1303,>0600,>1123 DATA >0580,>0206,>0001,>C0C5 DATA >0223,>0004,>06A0,>23CA DATA >C0C1,>0643,>05C3,>06A0 DATA >23CA,>0581,>6044,>3981 DATA >C186,>1611,>C187,>0608 DATA >15F5,>0606,>A184,>8180 DATA >150A,>05C3,>045A,>0200 DATA >0700,>0460,>2084,>0200 DATA >1C00,>0460,>2084,>0200 DATA >1400,>0460,>2084,>C01D DATA >C06D,>0002,>06A0,>20DC DATA >C0C1,>0603,>0223,>8300 DATA >D0D3,>0983,>160E,>C000 DATA >1622,>0202,>0008,>0204 DATA >834A,>C0C5,>06A0,>23CA DATA >CD01,>05C3,>0642,>15FA DATA >0380,>0643,>160F,>C000 DATA >1612,>C0C5,>05C3,>06A0 DATA >2406,>160B,>05C3,>06A0 DATA >23CA,>C101,>0201,>834A DATA >0460,>20CA,>06A0,>20F8 DATA >10F8,>0460,>2166,>0460 DATA >216E,>C81D,>2038,>C82D DATA >0002,>83E2,>C82D,>0004 DATA >2044,>02E0,>83E0,>C80B DATA >2040,>C020,>2044,>06A0 DATA >20DC,>C0C1,>0603,>0223 DATA >8300,>D0D3,>0983,>0603 DATA >1332,>0643,>164A,>C2A0 DATA >2038,>162D,>C0C5,>05C3 DATA >06A0,>2406,>9801,>2058 DATA >1620,>0206,>0008,>0204 DATA >834A,>C0C5,>06A0,>23CA DATA >CD01,>05C3,>0646,>15FA DATA >06A0,>22DA,>0225,>0004 DATA >C105,>C046,>06A0,>23E6 DATA >05C4,>D050,>0981,>06A0 DATA >23E6,>C2E0,>2040,>C820 DATA >203E,>830C,>02E0,>2038 DATA >0380,>0200,>0700,>C2E0 DATA >2040,>0460,>2084,>0200 DATA >1C00,>0460,>226E,>C08B DATA >0643,>16F3,>C0C5,>06A0 DATA >23CA,>C0C1,>06A0,>2406 DATA >1102,>0460,>226A,>C020 DATA >2038,>06A0,>211C,>6004 DATA >0A10,>A0C0,>06A0,>23CA DATA >0452,>06A0,>227E,>0206 DATA >834A,>CD83,>DDA0,>2058 DATA >DD84,>CD81,>C0C1,>1602 DATA >04D6,>1005,>0603,>06A0 DATA >2406,>0981,>C581,>C020 DATA >2044,>06A0,>22DA,>0460 DATA >225A,>C80B,>203A,>C805 DATA >203C,>C2E0,>601E,>069B DATA >C020,>2044,>C160,>203C DATA >D190,>0986,>C820,>830C DATA >203E,>C806,>830C,>C806 DATA >8350,>C2E0,>6012,>069B DATA >C020,>2044,>0206,>834A DATA >0204,>001C,>CD84,>DDA0 DATA >2058,>DD84,>C5A0,>831C DATA >C0A0,>830C,>1309,>C116 DATA >C0C0,>0583,>D073,>06A0 DATA >241A,>0584,>0602,>15FA DATA >C2E0,>6028,>069B,>C020 DATA >2044,>C160,>203C,>C2E0 DATA >203A,>045B,>C01D,>C06D DATA >0002,>06A0,>20DC,>C0C1 DATA >0603,>0223,>8300,>D0D3 DATA >0983,>0603,>1302,>0643 DATA >1623,>C000,>1628,>C02D DATA >0004,>C0C5,>05C3,>06A0 DATA >2406,>9801,>2058,>161D DATA >05C3,>06A0,>23CA,>C041 DATA >1307,>C181,>0601,>C0C1 DATA >06A0,>2406,>9050,>1A15 DATA >DC01,>1309,>C0C6,>0981 DATA >C141,>06A0,>2406,>DC01 DATA >0583,>0605,>15FA,>0380 DATA >06A0,>227E,>C02D,>0004 DATA >10E6,>0460,>2166,>0460 DATA >216E,>0200,>1300,>0460 DATA >2084,>06C3,>D803,>8C02 DATA >06C3,>D803,>8C02,>1000 DATA >D060,>8800,>06C1,>D060 DATA >8800,>06C1,>045B,>06C4 DATA >D804,>8C02,>06C4,>0264 DATA >4000,>D804,>8C02,>1000 DATA >D801,>8C00,>06C1,>D801 DATA >8C00,>06C1,>045B,>06C3 DATA >D803,>8C02,>06C3,>D803 DATA >8C02,>1000,>D060,>8800 DATA >045B,>06C4,>D804,>8C02 DATA >06C4,>0264,>4000,>D804 DATA >8C02,>1000,>D801,>8C00 DATA >045B,>C83E,>83E2,>02E0 DATA >83E0,>C80B,>204E,>C081 DATA >0281,>0040,>1B0A,>C0A1 DATA >6010,>0281,>0004,>1605 DATA >C0A2,>0002,>0692,>2466 DATA >1001,>0692,>02E0,>2038 DATA >C80B,>83F6,>0380,>0200 DATA >0B00,>0460,>2084,>02E0 DATA >83E0,>C80B,>204E,>06A0 DATA >000E,>02E0,>2038,>C80B DATA >83F6,>0380,>06A0,>24CA DATA >D82D,>0002,>8C00,>0380 DATA >06A0,>24CA,>D831,>8C00 DATA >0602,>16FC,>0380,>06A0 DATA >24D0,>DB60,>8800,>0002 DATA >0380,>06A0,>24D0,>DC60 DATA >8800,>0602,>16FC,>0380 DATA >C05D,>D82D,>0001,>8C02 DATA >0261,>8000,>D801,>8C02 DATA >0380,>0201,>4000,>1001 DATA >04C1,>C09D,>D820,>203D DATA >8C02,>E081,>D802,>8C02 DATA >C06D,>0002,>C0AD,>0004 DATA >045B ********************************************************** * EDITOR ASSEMBLER LOWER 8K SUPPORT * Data for Initialization of * Memory Expansion * LOW1 DATA >A55A,>2128,>2398,>225A LOW2 DATA >A000,>FFD7,>2676,>3F38 LOW3 DATA >0064,>2000,>2EAA,>2094 DATA >21C4,>2094,>2196,>2094,>21DE,>2094,>21F4 DATA >2094,>2200,>2094,>220E,>2094,>221A,>2094,>2228 DATA >209A,>22B2,>20DA,>23BA,>C80B,>2030,>D060 DATA >8349,>2060,>20FC,>132A,>C020,>8350,>1311,>06A0 DATA >2646,>101E,>0281,>3F38,>1319,>C001,>0202 DATA >834A,>8CB0,>1611,>8CB0,>160F,>8CB0,>160D,>C810 DATA >2022,>02E0,>20BA,>C020,>2022,>1309,>0690 DATA >02E0,>83E0,>C2E0,>2030,>045B,>0221,>0008,>10E4 DATA >0200,>0F00,>D800,>8322,>02E0,>83E0,>0460 DATA >00CE,>5820,>20FC,>8349,>02E0,>2094,>0380,>C83E DATA >83E2,>02E0,>83E0,>C80B,>20AA,>C081,>0281 DATA >8000,>1B07,>09C1,>0A11,>0A42,>09B2,>A0A1,>0CFA DATA >C092,>0692,>02E0,>2094,>C80B,>83F6,>0380 DATA >D060,>8373,>0981,>C87E,>8304,>F820,>20FC,>8349 DATA >02E0,>83E0,>C2E0,>2030,>045B,>02E0,>83E0 DATA >C80B,>20AA,>06A0,>000E,>02E0,>2094,>C80B,>83F6 DATA >0380,>06A0,>223A,>D82D,>0002,>8C00,>0380 DATA >06A0,>223A,>D831,>8C00,>0602,>16FC,>0380,>06A0 DATA >2240,>DB60,>8800,>0002,>0380,>06A0,>2240 DATA >DC60,>8800,>0602,>16FC,>0380,>C05D,>D82D,>0001 DATA >8C02,>0261,>8000,>D801,>8C02,>0380,>0201 DATA >4000,>1001,>04C1,>C09D,>D820,>2099,>8C02,>E081 DATA >D802,>8C02,>C06D,>0002,>C0AD,>0004,>045B DATA >0204,>834A,>C014,>C184,>04F6,>04F6,>C140,>1323 DATA >0740,>0203,>0040,>04F6,>04D6,>0280,>0064 DATA >1A13,>0280,>2710,>1A08,>0583,>C040,>04C0,>3C20 DATA >20FA,>D920,>83E3,>0003,>0583,>C040,>04C0 DATA >3C20,>20FA,>D920,>83E3,>0002,>D920,>83E1,>0001 DATA >D520,>83E7,>0545,>1101,>0514,>045B,>C17E DATA >53E0,>20FC,>C020,>8356,>C240,>0229,>FFF8,>0420 DATA >2114,>D0C1,>0983,>0704,>0202,>208C,>0580 DATA >0584,>80C4,>1306,>0420,>2114,>DC81,>9801,>20FE DATA >16F6,>C104,>1352,>0284,>0007,>154F,>04E0 DATA >83D0,>C804,>8354,>C804,>2036,>0584,>A804,>8356 DATA >C820,>8356,>2038,>02E0,>83E0,>04C1,>020C DATA >0F00,>C30C,>1301,>1E00,>022C,>0100,>04E0,>83D0 DATA >028C,>2000,>1332,>C80C,>83D0,>1D00,>0202 DATA >4000,>9812,>20FF,>16EE,>A0A0,>20A4,>1003,>C0A0 DATA >83D2,>1D00,>C092,>13E6,>C802,>83D2,>05C2 DATA >C272,>D160,>8355,>1309,>9C85,>16F2,>0985,>0206 DATA >208C,>9CB6,>16ED,>0605,>16FC,>0581,>C801 DATA >203A,>C809,>2034,>C80C,>2032,>0699,>10E2,>1E00 DATA >02E0,>209A,>C009,>0420,>2114,>09D1,>1604 DATA >0380,>02E0,>209A,>04C1,>06C1,>D741,>F3E0,>20FC DATA >0380,>C80B,>2030,>02E0,>20BA,>0420,>2124 DATA >02E0,>83E0,>1303,>C2E0,>2030,>045B,>D820,>20BA DATA >8322,>0460,>00CE,>04E0,>2022,>53E0,>20FC DATA >C020,>8356,>0420,>2120,>0008,>1332,>0220,>FFF7 DATA >0201,>0200,>0420,>210C,>0580,>C800,>202E DATA >C1E0,>2024,>C147,>04CC,>06A0,>25E0,>0283,>0001 DATA >1624,>058C,>04C3,>1023,>0283,>0046,>161E DATA >04C2,>06A0,>262E,>0283,>003A,>16F7,>C020,>202E DATA >0600,>0201,>0100,>0420,>210C,>06A0,>25E0 DATA >C020,>2022,>1307,>06A0,>2646,>1005,>CB4E,>0016 DATA >C3A0,>2022,>0380,>D740,>F3E0,>20FC,>0380 DATA >06A0,>25C2,>04C4,>D123,>2662,>0974,>C808,>202C DATA >06A0,>2594,>0464,>23F8,>0580,>0240,>FFFE DATA >C120,>2024,>A100,>1808,>8804,>2026,>1B05,>C160 DATA >2024,>C804,>2024,>100A,>C120,>2028,>A100 DATA >8804,>202A,>140C,>C160,>2028,>C804,>2028,>C1C5 DATA >0209,>0008,>06A0,>262E,>0609,>16FC,>10B6 DATA >0200,>0800,>10CC,>A005,>C800,>2022,>10AF,>A800 DATA >202C,>13AC,>0200,>0B00,>10C2,>A005,>C1C0 DATA >10A6,>A005,>DDC0,>DDE0,>20DB,>10A1,>A005,>06A0 DATA >2566,>C000,>1316,>0226,>FFF8,>8106,>1B02 DATA >0514,>1096,>8594,>16F8,>89A4,>0002,>0002,>16F4 DATA >89A4,>0004,>0004,>16F0,>C0E6,>0006,>C250 DATA >C403,>C009,>16FC,>0224,>0008,>C804,>202A,>10EA DATA >A005,>06A0,>2566,>0226,>FFF8,>8106,>13E3 DATA >C296,>1501,>050A,>8294,>16F7,>89A4,>0002,>0002 DATA >16F3,>89A4,>0004,>0004,>16EF,>C296,>1516 DATA >C0E6,>0006,>C253,>C4C0,>C0C9,>16FC,>C246,>6244 DATA >C286,>022A,>0008,>C0C6,>0643,>064A,>C693 DATA >0649,>16FB,>0224,>0008,>C804,>202A,>10D9,>CB44 DATA >0002,>0200,>0C00,>0460,>2432,>0460,>2494 DATA >C28B,>0209,>0006,>C1A0,>202A,>0226,>FFF8,>C106 DATA >8806,>2028,>1AF3,>C806,>202A,>06A0,>262E DATA >DDA0,>20E1,>0609,>16FA,>C580,>0206,>4000,>045A DATA >C28B,>04C0,>C30C,>1308,>06A0,>262E,>D020 DATA >20E1,>06A0,>262E,>A003,>045A,>0209,>0004,>06A0 DATA >262E,>06A0,>25C2,>0A40,>A003,>0609,>16F8 DATA >045A,>0223,>FFD0,>0283,>000A,>1A05,>0223,>FFF9 DATA >0283,>0019,>1B01,>045B,>0200,>0A00,>0460 DATA >2432,>02E0,>83E0,>0200,>2032,>C330,>C270,>C830 DATA >8354,>C830,>8356,>C050,>1D00,>9820,>4000 DATA >20FF,>161D,>0699,>101B,>1E00,>02E0,>20DA,>C020 DATA >202E,>0201,>20DB,>0202,>0004,>0420,>2118 DATA >7000,>0950,>1610,>0982,>C001,>0201,>203C,>0420 DATA >2118,>04C8,>0602,>11D7,>D0F1,>0983,>A203 DATA >045B,>02E0,>20DA,>04C0,>06C0,>0460,>2432,>0201 DATA >3F40,>0221,>FFF8,>C011,>1105,>8060,>202A DATA >16F9,>05CB,>045B,>0200,>0D00,>045B,>2D52,>5163 DATA >6483,>8455,>045C,>5B5F,>5EF0,>F003,>F0F0 DATA >4700,>00C8,>3F38 LOW4 DATA >5554,>4C54,>4142,>2022,>5041,>4420,>2020,>8300 DATA >4750,>4C57,>5320,>83E0,>534F,>554E,>4420 DATA >8400,>5644,>5052,>4420,>8800,>5644,>5053,>5441 DATA >8802,>5644,>5057,>4420,>8C00,>5644,>5057 DATA >4120,>8C02,>5350,>4348,>5244,>9000,>5350,>4348 DATA >5754,>9400,>4752,>4D52,>4420,>9800,>4752 DATA >4D52,>4120,>9802,>4752,>4D57,>4420,>9C00,>4752 DATA >4D57,>4120,>9C02,>5343,>414E,>2020,>000E DATA >584D,>4C4C,>4E4B,>2104,>4B53,>4341,>4E20,>2108 DATA >5653,>4257,>2020,>210C,>564D,>4257,>2020 DATA >2110,>5653,>4252,>2020,>2114,>564D,>4252,>2020 DATA >2118,>5657,>5452,>2020,>211C,>4453,>524C DATA >4E4B,>2120,>4C4F,>4144,>4552,>2124,>4750,>4C4C DATA >4E4B,>2100 *********************************************************** * * RXB Character set *********************************************************** CHARS BYTE >00,>10,>10,>10,>10,>10,>00,>10 * ! 33 BYTE >00,>50,>50,>50,>00,>00,>00,>00 * " 34 BYTE >00,>50,>50,>F8,>50,>F8,>50,>50 * # 35 BYTE >00,>20,>78,>A0,>70,>28,>F0,>20 * $ 36 BYTE >00,>C0,>C8,>10,>20,>40,>98,>18 * % 37 BYTE >00,>40,>A0,>A0,>40,>A8,>90,>68 * & 38 BYTE >00,>C0,>40,>80,>00,>00,>00,>00 * ' 39 BYTE >00,>08,>10,>20,>20,>20,>10,>08 * ( 40 BYTE >00,>10,>08,>04,>04,>04,>08,>10 * ) 41 BYTE >00,>00,>28,>10,>7C,>10,>28,>00 * * 42 BYTE >00,>00,>10,>10,>7C,>10,>10,>00 * + 43 BYTE >00,>00,>00,>00,>00,>60,>20,>40 * , 44 BYTE >00,>00,>00,>00,>F8,>00,>00,>00 * - 45 BYTE >00,>00,>00,>00,>00,>00,>60,>60 * . 46 BYTE >00,>00,>08,>10,>20,>40,>80,>00 * / 47 BYTE >00,>70,>88,>98,>A8,>C8,>88,>70 * 0 48 BYTE >00,>20,>60,>20,>20,>20,>20,>70 * 1 49 BYTE >00,>70,>88,>08,>30,>40,>80,>F8 * 2 50 BYTE >00,>70,>88,>08,>30,>08,>88,>70 * 3 51 BYTE >00,>10,>30,>50,>90,>F8,>10,>10 * 4 52 BYTE >00,>F0,>80,>80,>F0,>08,>88,>70 * 5 53 BYTE >00,>70,>80,>80,>F0,>88,>88,>70 * 6 54 BYTE >00,>F8,>08,>10,>20,>40,>40,>40 * 7 55 BYTE >00,>70,>88,>88,>70,>88,>88,>70 * 8 56 BYTE >00,>70,>88,>88,>78,>08,>88,>70 * 9 57 BYTE >00,>00,>60,>60,>00,>60,>60,>00 * : 58 BYTE >00,>00,>60,>60,>00,>60,>20,>40 * ; 59 BYTE >00,>08,>10,>20,>40,>20,>10,>08 * < 60 BYTE >00,>00,>7C,>00,>00,>7C,>00,>00 * = 61 BYTE >00,>20,>10,>08,>04,>08,>10,>20 * > 62 BYTE >00,>70,>88,>10,>20,>20,>00,>20 * ? 63 BYTE >00,>38,>44,>5C,>54,>5C,>40,>38 * @ 64 BYTE >00,>70,>88,>88,>F8,>88,>88,>88 * A 65 BYTE >00,>F0,>48,>48,>70,>48,>48,>F0 * B 66 BYTE >00,>70,>88,>80,>80,>80,>88,>70 * C 67 BYTE >00,>F0,>48,>48,>48,>48,>48,>F0 * D 68 BYTE >00,>F8,>80,>80,>F0,>80,>80,>F8 * E 69 BYTE >00,>F8,>80,>80,>F0,>80,>80,>80 * F 70 BYTE >00,>70,>88,>80,>80,>98,>88,>78 * G 71 BYTE >00,>88,>88,>88,>F8,>88,>88,>88 * H 72 BYTE >00,>F8,>20,>20,>20,>20,>20,>F8 * I 73 BYTE >00,>08,>08,>08,>08,>08,>88,>70 * J 74 BYTE >00,>88,>90,>A0,>C0,>A0,>90,>88 * K 75 BYTE >00,>80,>80,>80,>80,>80,>80,>F8 * L 76 BYTE >00,>88,>D8,>A8,>A8,>88,>88,>88 * M 77 BYTE >00,>88,>88,>C8,>A8,>98,>88,>88 * N 78 BYTE >00,>70,>88,>88,>88,>88,>88,>70 * O 79 BYTE >00,>F0,>88,>88,>88,>F0,>80,>80 * P 80 BYTE >00,>70,>88,>88,>88,>A8,>90,>68 * Q 81 BYTE >00,>F0,>88,>88,>F0,>A0,>90,>88 * R 82 BYTE >00,>70,>88,>80,>70,>08,>88,>70 * S 83 BYTE >00,>F8,>20,>20,>20,>20,>20,>20 * T 84 BYTE >00,>44,>44,>44,>44,>44,>44,>38 * U 85 BYTE >00,>44,>44,>44,>28,>28,>10,>10 * V 86 BYTE >00,>88,>88,>88,>88,>A8,>A8,>50 * W 87 BYTE >00,>88,>88,>50,>20,>50,>88,>88 * X 88 BYTE >00,>88,>88,>88,>50,>20,>20,>20 * Y 89 BYTE >00,>F8,>08,>10,>20,>40,>80,>F8 * Z 90 BYTE >00,>78,>40,>40,>40,>40,>40,>78 * [ 91 BYTE >00,>00,>80,>40,>20,>10,>08,>00 * \ 92 BYTE >00,>F0,>10,>10,>10,>10,>10,>F0 * ] 93 BYTE >00,>20,>50,>88,>00,>00,>00,>00 * ^ 94 BYTE >00,>00,>00,>00,>00,>00,>00,>FF * _ 95 BYTE >00,>18,>10,>08,>00,>00,>00,>00 * ` 96 BYTE >00,>00,>00,>60,>10,>70,>90,>68 * a 97 BYTE >00,>00,>40,>40,>70,>48,>48,>B0 * b 98 BYTE >00,>00,>00,>60,>90,>80,>90,>60 * c 99 BYTE >00,>00,>10,>10,>70,>90,>90,>68 * d 100 BYTE >00,>00,>00,>60,>90,>E0,>80,>70 * e 101 BYTE >00,>00,>30,>40,>E0,>40,>40,>40 * f 102 BYTE >00,>00,>00,>70,>90,>70,>10,>60 * g 103 BYTE >00,>00,>80,>80,>E0,>90,>90,>90 * h 104 BYTE >00,>00,>20,>00,>20,>20,>20,>70 * i 105 BYTE >00,>00,>10,>10,>10,>10,>90,>60 * j 106 BYTE >00,>00,>80,>90,>A0,>C0,>A0,>90 * k 107 BYTE >00,>00,>60,>20,>20,>20,>20,>70 * l 108 BYTE >00,>00,>00,>D0,>A8,>A8,>A8,>A8 * m 109 BYTE >00,>00,>00,>B0,>48,>48,>48,>48 * n 110 BYTE >00,>00,>00,>60,>90,>90,>90,>60 * o 111 BYTE >00,>00,>F0,>48,>48,>70,>40,>40 * p 112 BYTE >00,>00,>78,>90,>90,>70,>10,>10 * q 113 BYTE >00,>00,>00,>B0,>C8,>80,>80,>80 * r 114 BYTE >00,>00,>00,>70,>80,>70,>08,>F0 * s 115 BYTE >00,>00,>40,>E0,>40,>40,>50,>20 * t 116 BYTE >00,>00,>00,>90,>90,>90,>90,>68 * u 117 BYTE >00,>00,>00,>88,>88,>88,>50,>20 * v 118 BYTE >00,>00,>00,>88,>88,>A8,>A8,>50 * w 119 BYTE >00,>00,>00,>88,>50,>20,>50,>88 * x 120 BYTE >00,>00,>00,>48,>48,>38,>08,>70 * y 121 BYTE >00,>00,>00,>F8,>10,>20,>40,>F8 * z 122 BYTE >00,>18,>20,>20,>40,>20,>20,>18 * { 123 BYTE >00,>20,>20,>20,>00,>20,>20,>20 * | 124 BYTE >00,>C0,>20,>20,>10,>20,>20,>C0 * } 125 BYTE >00,>00,>00,>40,>A8,>10,>00,>00 * ~ 126 *********************************************************** END Quote Link to comment Share on other sites More sharing options...
+Lee Stewart Posted June 15, 2021 Share Posted June 15, 2021 11 hours ago, RXB said: Did a mod to use FAC as buffer and not used VDP to save VDP. What do you think? Working on it. I probably won’t be able to do much until this evening. ...lee 1 1 Quote Link to comment Share on other sites More sharing options...
+Lee Stewart Posted June 16, 2021 Share Posted June 16, 2021 (edited) On 6/15/2021 at 1:36 AM, RXB said: Did a mod to use FAC as buffer and not used VDP to save VDP. What do you think? I am confused by your code. I can correct it, but I think you will be better served by my code, which uses two VDP address writes for each row roundtrip to/from scratchpad RAM at FAC, whereas your code is still using two VDP address writes for each and every byte, which does not change the code’s inefficiency. By using FAC as a RAM column buffer, you are only saving 24 VDP address writes for each left or right roll of the screen. Since there is, practically, only enough room to buffer one row in scratchpad RAM, it makes the most sense to me to do multibyte transfers, one row at a time, from VRAM to RAM and back. This involves only one VDP address write for each direction. For left and right rolls of the screen, there is no need for a column buffer that requires 24 VDP address writes each way because the column roll can be effected with each row transfer using only three VDP address writes: Copy next row to FAC (1 VDP address write). Copy rolled-out byte to rolled-in column (1 VDP address write). Copy 31 bytes to new column offset (1 VDP address write). Repeat (1) – (3) for each row 23 more times (69 VDP address writes). Sum of above = 72 VDP address writes). For up and down rolls of the screen, the rolled-out row needs to be buffered for as long as the remaining rows are processed. Since there is no room for 2 rows in scratchpad RAM, we lose a little efficiency by needing to use a VRAM row buffer: Copy rolled-out row to FAC (1 VDP address write). Copy FAC buffer to VDP buffer (1 VDP address write). Copy next row to FAC (1 VDP address write). Copy FAC to next row offset (1 VDP address write). Repeat (3) and (4) for 22 more rows (44 VDP address writes). Copy VDP buffer to FAC (1 VDP address write). Copy FAC to rolled-in row (1 VDP address write). Sum of the above = 50 VDP address writes. ...lee Edited June 16, 2021 by Lee Stewart Clarification of VDP Address Writes 3 1 Quote Link to comment Share on other sites More sharing options...
Asmusr Posted June 16, 2021 Share Posted June 16, 2021 @Lee Stewart you could make your code even faster if you had two MOVB instructions after each other in your loops and used DECT. You would need to handle the edge case when you only move 31 bytes by moving 30 bytes and adding an additional MOVB after the loop. 3 Quote Link to comment Share on other sites More sharing options...
RXB Posted June 16, 2021 Share Posted June 16, 2021 12 minutes ago, Asmusr said: @Lee Stewart you could make your code even faster if you had two MOVB instructions after each other in your loops and used DECT. You would need to handle the edge case when you only move 31 bytes by moving 30 bytes and adding an additional MOVB after the loop. Got any code to show this? Like when Lee says WRITE what does he mean? WRITE the ADDRESS or BYTE or what? Quote Link to comment Share on other sites More sharing options...
+Lee Stewart Posted June 16, 2021 Share Posted June 16, 2021 2 hours ago, RXB said: Like when Lee says WRITE what does he mean? WRITE the ADDRESS or BYTE or what? If you are talking about my last post, every last use of the word ‘write’ refers explicitly to an address write, which, as you well know, requires 2 MOVB instructions, one for the LSB and one for the MSB of the VRAM address being written. If you are referring to some other use I made of ‘write’, please be more specific. ...lee 1 1 Quote Link to comment Share on other sites More sharing options...
+Lee Stewart Posted June 17, 2021 Share Posted June 17, 2021 7 hours ago, Asmusr said: @Lee Stewart you could make your code even faster if you had two MOVB instructions after each other in your loops and used DECT. You would need to handle the edge case when you only move 31 bytes by moving 30 bytes and adding an additional MOVB after the loop. I think I may try inlining all of the VRAM reads and writes as well. It will likely bloat the code a bit, but I bet not by much. ...lee 2 1 Quote Link to comment Share on other sites More sharing options...
RXB Posted June 17, 2021 Share Posted June 17, 2021 I have drawn diagrams of what you have told me to visualize what you are saying. Very informative and helpful. 2 Quote Link to comment Share on other sites More sharing options...
+Lee Stewart Posted June 17, 2021 Share Posted June 17, 2021 2 hours ago, Lee Stewart said: I think I may try inlining all of the VRAM reads and writes as well. It will likely bloat the code a bit, but I bet not by much. I decided not to inline the VRAM data reads and writes for this iteration but did use @Asmusr’s suggestion of using DECT with pairs of VRAM data reads and writes. It turns out that, with one other change to the left/right rolls, I do not need to do any single-byte data reads or writes—not a single one! All I needed to do was to do the column roll in the RAM buffer. With that change, all of the VRAM data reads and writes are 32 bytes. This allowed hoisting the count assignment of (always) 32 to the new VRAM row read and write routines. Every screen roll is now 50 VDP address reads/writes. All of this also reduced the code to 342 bytes and resulted in 24 % faster rolls than my last code and nearly 3 times (2.8) faster than the RXB (all) single-byte VRAM data reads and writes. Here is the code: Spoiler *********************************************************** AORG >6000 TITL 'RXB ROM3' UNUSED DATA >0000,>0000,>0000,>0000 DATA >0000,>0000,>0000,>0000 ************************************************************ * XML table number 7 for RXB ROM3 - must have * * it's origin at >6010 * ************************************************************ * 0 1 2 3 4 5 6 DATA RROLL,LROLL,UROLL,DROLL,>0000,>0000,>0000 * 7 8 9 A B C D DATA >0000,>0000,>0000,>0000,>0000,>0000,>0000 * E F DATA >0000,>0000 ************************************************************ * XML table number 8 for RXB ROM3 - must have * * it's origin at >6030 * ************************************************************ * 0 1 2 3 4 5 6 7 DATA >0000,>0000,>0000,>0000,>0000,>0000,>0000,>0000 * 8 9 A B C D E F DATA >0000,>0000,>0000,>0000,>0000,>0000,>0000,>0000 GR0LB EQU >83E1 * GPLWS R0 LSB FAC EQU >834A * RAM line buffer SAVRTN EQU >836C * free space after RAM line buffer VBUFF EQU >03C0 * line buffer in VRAM VDPRD EQU >8800 * VDP Read Data address VDPWD EQU >8C00 * VDP Write Data address * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Write VRAM address * Expects address in R0 * * BL here for writing data * VWADDW ORI R0,>4000 * set to write VRAM data * * BL here for reading data * VWADD MOVB @GR0LB,*R15 * write LSB of R0 to VDPWA MOVB R0,*R15 * write MSB of R0 to VDPWA ANDI R0,>3FFF * ensure R0 returned intact RT * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * The following utilities expect * R0 = VRAM address of row * R1 = RAM buffer address * * R2 and R10 will be destroyed * * Copy 1 row of 32 bytes from VRAM (R0) to RAM (R1) * VRROW MOV R11,R10 * save return BL @VWADD * write out VRAM read address LI R2,32 * read 1 row VRROW1 MOVB @VDPRD,*R1+ * read next VRAM byte to RAM MOVB @VDPRD,*R1+ * read next VRAM byte to RAM DECT R2 * dec count by 2 JNE VRROW1 * repeat if not done B *R10 * return to caller * * Copy 1 row of 32 bytes from RAM (R1) to VRAM (R0) * VWROW MOV R11,R10 * save return BL @VWADDW * write out VRAM write address LI R2,32 * write one row VWROW1 MOVB *R1+,@VDPWD * write next VRAM byte from RAM MOVB *R1+,@VDPWD * write next VRAM byte from RAM DECT R2 * dec count by 2 JNE VWROW1 * repeat if not done B *R10 * return to caller * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * RROLL * RROLL MOV R11,@SAVRTN * save return address CLR R0 * set to screen start LI R3,24 * rows to roll * Write row to RAM buffer RROLLP LI R1,FAC+1 * RAM buffer+1 for roll-right positions BL @VRROW * copy row to RAM buffer 2 bytes at a time * Copy last column before first in RAM buffer MOVB @FAC+32,@FAC * copy roll-out byte to roll-in position * Copy rolled row back to screen (R0 still has correct location) LI R1,FAC * reset RAM buffer pointer BL @VWROW * copy rolled line * Process next row AI R0,32 * next row DEC R3 * dec row count JNE RROLLP * roll next row if not done MOV @SAVRTN,R11 * restore return address RT * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * LROLL * LROLL MOV R11,@SAVRTN * save return address CLR R0 * set to screen start LI R3,24 * rows to roll * Write row to RAM buffer LROLLP LI R1,FAC * RAM buffer+1 for roll-left positions BL @VRROW * copy row to RAM buffer 2 bytes at a time * Copy first column after last in RAM buffer MOVB @FAC,@FAC+32 * copy roll-out byte to roll-in position * Copy rolled row back to screen (R0 still has correct location) LI R1,FAC+1 * reset RAM buffer pointer BL @VWROW * copy rolled line 2 bytes at a time * Process next row AI R0,32 * next row DEC R3 * dec row count JNE LROLLP * roll next row if not done MOV @SAVRTN,R11 * restore return address RT * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * UROLL * UROLL MOV R11,@SAVRTN * save return address CLR R0 * set to screen start LI R3,23 * rows to roll (all but 1st) * Write first row to RAM buffer LI R1,FAC * set RAM buffer BL @VRROW * copy row to RAM buffer 2 bytes at a time * Copy RAM buffer to VRAM buffer LI R0,VBUFF * set VRAM dest to VBUFF LI R1,FAC * set RAM buffer BL @VWROW * copy row to VBUFF 2 bytes at a time * Start copy loop at 2nd row LI R0,32 * point to 2nd row * Write row to RAM buffer UROLLP LI R1,FAC * set RAM buffer BL @VRROW * copy row to RAM buffer 2 bytes at a time * Copy to previous row AI R0,-32 * back up 1 row LI R1,FAC * reset RAM buffer pointer BL @VWROW * copy to previous row 2 bytes at a time * Process next row AI R0,64 * next row DEC R3 * dec row count JNE UROLLP * roll next row if not done * Copy saved row to RAM LI R0,VBUFF * set VRAM source LI R1,FAC * set RAM buffer BL @VRROW * copy row to RAM buffer 2 bytes at a time * Copy saved row to last row LI R0,736 * point to last row LI R1,FAC * reset RAM buffer pointer BL @VWROW * copy to last row 2 bytes at a time MOV @SAVRTN,R11 * restore return address RT * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * DROLL * DROLL MOV R11,@SAVRTN * save return address LI R0,736 * set to last row LI R3,23 * rows to roll (all but last) * Write last row to RAM buffer LI R1,FAC * set RAM buffer BL @VRROW * copy row to RAM buffer 2 bytes at a time * Copy RAM buffer to VRAM buffer LI R0,VBUFF * set VRAM dest to VBUFF LI R1,FAC * set RAM buffer BL @VWROW * copy row to VBUFF 2 bytes at a time * Start copy loop at 2nd-to-last row LI R0,704 * point to row 22 * Write row to RAM buffer DROLLP LI R1,FAC * set RAM buffer BL @VRROW * copy row to RAM buffer 2 bytes at a time * Copy to next row AI R0,32 * down 1 row LI R1,FAC * reset RAM buffer pointer BL @VWROW * copy to next row 2 bytes at a time * Process next row AI R0,-64 * back up 2 rows DEC R3 * dec row count JNE DROLLP * roll next row if not done * Copy saved row to RAM LI R0,VBUFF * set VRAM source LI R1,FAC * set RAM buffer BL @VRROW * copy row to RAM buffer 2 bytes at a time * Copy saved row to first row CLR R0 * point to first row LI R1,FAC * reset RAM buffer pointer BL @VWROW * copy to first row 2 bytes at a time MOV @SAVRTN,R11 * restore return address RT END The up and down rolls work as before, but the right and left rolls now work as follows: Right Roll— Move first row from VRAM to FAC+1. Move byte at FAC+32 to FAC, effecting the right roll for this row. Move 32 bytes from FAC to original row location in VRAM. Repeat (1) – (3) 23 more times to complete right roll of screen. Left Roll— Move first row from VRAM to FAC. Move byte at FAC to FAC+32, effecting the left roll for this row. Move 32 bytes from FAC+1 to original row location in VRAM. Repeat (1) – (3) 23 more times to complete left roll of screen. If I worked a little harder, I could probably combine the up/down routines as well as the right/left routines—the pairs are practically identical, but, right now, I think the above code is pretty solid. ...lee 5 Quote Link to comment Share on other sites More sharing options...
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