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My Atari XEGS Project


boisy

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Rybags,

 

Tried getting the code to the simplest incarnation and still am getting the dark green screen. I suspect something clock related, but cannot say for sure until I get myself a scope. I consulted with Gary on the design and it appears that we need to invert /HALT when tying it into the TSC of the '09. I modified the satellite board accordingly, but am getting the same results.

 

So for now, everything's on hold waiting for the acquisition of a scope.

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Isn't the RESET vector at $FFFE? (not $FFDE)

 

Is this one of the things that you changed?

 

If you are going to buy a scope, a logic analyzer may be more useful.

 

Bob

 

Bob,

 

Yes, that was one of the typos I fixed.

 

I hear you on the logic analyzer. Will be making some purchasing decisions soon.

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One thing to try - I've got doubts it'll make any difference.

 

The XL OS has a big delay loop on Reset - probably lasts about .1 seconds or so.

 

Maybe try doing that early on (before cleario)

 

The /Halt mechanism is vital - Antic does Refresh cycles every scanline so it has to be right.

 

As a test to see if you're at least getting a few instructions executed you might try the colour change for Background right at the beginning (before any delays). That's the store operation to $D01A. You might luck out and occasionally get startup before Antic has a chance to do any halt operations.

 

It could also serve as a handy debug aid - change the background colour on each phase of your initialization (remembering cleario will set it back to black)

 

Format for colour registers - high nybble is colour, low nybble is brightness (bit 0 ignored).

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One thing to try - I've got doubts it'll make any difference.

 

The XL OS has a big delay loop on Reset - probably lasts about .1 seconds or so.

 

Maybe try doing that early on (before cleario)

 

The /Halt mechanism is vital - Antic does Refresh cycles every scanline so it has to be right.

 

As a test to see if you're at least getting a few instructions executed you might try the colour change for Background right at the beginning (before any delays). That's the store operation to $D01A. You might luck out and occasionally get startup before Antic has a chance to do any halt operations.

 

It could also serve as a handy debug aid - change the background colour on each phase of your initialization (remembering cleario will set it back to black)

 

Format for colour registers - high nybble is colour, low nybble is brightness (bit 0 ignored).

 

I tried this very thing... basically did this:

 

orcc #$50 ; mask interrupts

lda #$55 ; load some color value

sta $D10A ; store to set color

xxx jmp xxx

 

And makes no difference, as you expected.

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One thing to try - I've got doubts it'll make any difference.

 

The XL OS has a big delay loop on Reset - probably lasts about .1 seconds or so.

 

Maybe try doing that early on (before cleario)

 

The /Halt mechanism is vital - Antic does Refresh cycles every scanline so it has to be right.

 

As a test to see if you're at least getting a few instructions executed you might try the colour change for Background right at the beginning (before any delays). That's the store operation to $D01A. You might luck out and occasionally get startup before Antic has a chance to do any halt operations.

 

It could also serve as a handy debug aid - change the background colour on each phase of your initialization (remembering cleario will set it back to black)

 

Format for colour registers - high nybble is colour, low nybble is brightness (bit 0 ignored).

 

I tried this very thing... basically did this:

 

orcc #$50 ; mask interrupts

lda #$55 ; load some color value

sta $D10A ; store to set color

xxx jmp xxx

 

And makes no difference, as you expected.

 

I transposed the numbers in the message. It's $D01A in the source, and I've verified the same results.

 

Thanks for the pointer though.

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Cool. I didn't realise they came that cheap. Might have to look into one myself.

There are actually cheaper ones out there but they don't come in a CNC machined aluminum case.

 

What would be real nice once this gets off the ground is a dual CPU + dual OS ROM board, with software ability to reset and switch between the 6502/6809.

That was pretty much what I was thinking Hmmmm... maybe a 65815 instead of 6502. :D

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Cool. I didn't realise they came that cheap. Might have to look into one myself.

 

What would be real nice once this gets off the ground is a dual CPU + dual OS ROM board, with software ability to reset and switch between the 6502/6809.

 

The goal is to design this board in such a way that it can adapt the 6809 into a number of 6502 based computers, not just the Atari XE. I'm eyeing the Commodore 64 as another possible candidate. But first things first.

 

 

I agree that a dual CPU satellite board would be the ticket. I'm wondering what kind of reception this type of product would get. There certainly seems to be interest here on this thread, but in the general Atari community, I'm not sure.

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@JamesD,

For the 65C816, look in another topic. Ít's been done already.

 

@boisy

About the how to put a standard 6502 in any XL/XE, have a look here: http://www.b-pahl.de/atari8bit/65c02/65c02.html

The schematics I used there, came from the Atari 800 board.

So I think it's safe to assume that what they did to make the 6502C Sally chip is just integrate the FF and gates into the CPU.

 

BR/

Guus

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My $.02...

 

With only 16 bits, you will not be able to decode a 16-bit address bus and see an 8-bit data bus along with control signals. The unit I use has 34 inputs. Also, take a look at the connection options - a 40-pin clip is really nice. So is a 500MHZ clock.

 

This unit is $389 - well worth the price. Don't buy something that is of limited use.

 

Bob

 

 

post-14708-0-45575400-1327938634_thumb.jpg

 

I've been needing to get a logic analyzer for other projects, and this one is enough for me to pull the trigger. So, I just ordered one of these: http://www.saleae.com/Logic16

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My $.02...

 

With only 16 bits, you will not be able to decode a 16-bit address bus and see an 8-bit data bus along with control signals. The unit I use has 34 inputs. Also, take a look at the connection options - a 40-pin clip is really nice. So is a 500MHZ clock.

 

This unit is $389 - well worth the price. Don't buy something that is of limited use.

 

Bob

 

 

post-14708-0-45575400-1327938634_thumb.jpg

 

I've been needing to get a logic analyzer for other projects, and this one is enough for me to pull the trigger. So, I just ordered one of these: http://www.saleae.com/Logic16

 

500MHz sample rate? Holy cow. How long can you sustain a capture session?

 

That's quite impressive. I've cancelled my Logic16 order and am trying to get in touch with the Intronix folks.

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It captures (I think) a couple of thousand cycles pre-trigger, post trigger, and anywhere in-between. You don't have to use 500MHZ, of course. It has a variety of clock speeds as well as using an input as a clock. I use 200MHZ when I want to see race conditions or signal bounce kind of things. If I am tracing instructions, I use 02 clock.

 

Use the web site on the unit - pctestinstruments.com

 

Bob

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It captures (I think) a couple of thousand cycles pre-trigger, post trigger, and anywhere in-between. You don't have to use 500MHZ, of course. It has a variety of clock speeds as well as using an input as a clock. I use 200MHZ when I want to see race conditions or signal bounce kind of things. If I am tracing instructions, I use 02 clock.

 

Use the web site on the unit - pctestinstruments.com

 

Bob

 

Based on your recommendation (and the recommendation of a trusted colleague who I also showed this to) I've gone ahead and ordered this device. Thanks for the recommendation.

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Someone asked about the availability of the 6809 these days.

 

It's apparently still available from several 3rd party sources. Here's one source:

 

http://www.nteinc.com/specs/6800to6899/pdf/nte6809_e.pdf

 

The part is sold at Newark and Digikey, among others. A bit pricey at $21, but they can be found cheaper at Jameco.

 

That doesn't include the 6309E which can still be found as well.

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Well, I got the LogicPort in... fantastic device.

 

I hooked it up to the PHI0, PHI1, PHI2 and /HALT lines of the 6502C in the Atari XEGS just to see what those lines are doing normally. What I see is mystifying. It appears that periodically, there is no clock. It's not related to the /HALT line, but maybe to another line that I'm not monitoring.

 

I then hooked the other set of probes up to the 6809E on the CoCo 3's E and Q lines just to make sure I wasn't seeing a glitch. Sampling on the E and Q lines show perfect waves every time.

 

Is there a reason why PHI0 would be stopped to the processor periodically?

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Sounds a bit weird to me - can you post up a capture pic?

 

Any "clock halting" should be internal to the 6502C as far as I see it. Only the early 400/800 used a standard 6502 with an external circuit that halted the clock going to the CPU.

 

Sure. Check out the clip attached.

 

Note I am capturing 5 signals: PHI0, PH1, PH2, RDY and /HALT. RDY is high and /HALT is high during the period where PHI0 stays high... which drives the other two clock lines high.

 

I'm pretty sure my probes are correct. Double checked and they are secure. Like I said, I can continue sampling and get these clock stoppages often.

PH0, PH1, PH2, RDY and /HALT on 6502C

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