Custom bankswitching and ram

[wallaby]

I've managed to get a custom cartridge working and now I'm interested in how to utilize more ROM and RAM. I'm not clear on how this is done, so I was hoping someone could correct any misconceptions.

 

Bank-switching:

 

For more ROM, you would bank switch more code into the Atari's 4k window.

 

You can do this by using a custom logic chip (CPLA?) to monitor the address bus and when the program triggers the right pattern, the CPLA knows to change the bank to whatever logic you have set that bank to. For example, 10101010101 could mean switch to bank 2? Prior to this, you'd store the program counter in RAM so you know where to return to?

 

RAM:

 

For reading and writing RAM, could you use the same CPLA to monitor the custom logic on the address bus? You would need commands for writing and reading RAM and you'd have to store the RAM address in the Atari's internal memory before calling the 'function'. So, you could store two bytes in the Atari RAM for your custom address and depending whether it is a read or a write, another byte for the data to store?

 

Is it worse than that or am I over complicating it?

 

 

[CPUWIZ]

Right track. You may want to take a peek at this document.

[ZackAttack]

Programmable logic chip would be the easiest thing to prototype with. If you have enough I/O pins on the logic chip I'd connect the full VCS address and data buses to it as inputs. Depending on what your smallest bank size is you will connect that many VCS address bits directly to the eeprom. The remaining eeprom address bits should be driven by the logic chip.

[wallaby]

Programmable logic chip would be the easiest thing to prototype with. If you have enough I/O pins on the logic chip I'd connect the full VCS address and data buses to it as inputs. Depending on what your smallest bank size is you will connect that many VCS address bits directly to the eeprom. The remaining eeprom address bits should be driven by the logic chip.

 

So I could have 12 + 8: 20 bits for logic? How does the PLA know which direction the data is coming from? (Sorry, these are obviously very newb questions.)

 

I imagine it works like this: [Atari] -> [PLA pass-through except inverting A12] -> [EEPROM] -> [PLA logic] -> [sRAM possibly] -> [Atari]

 

Do I need to worry about the PLA CE or does it turn on at the same time as the EEPROM?

 

I'm also confused about timing and bus contention. Trying to learn by doing.