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Level42

I want to learn ANTIC / GTIA :)

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OK. So Sally can be isolated from the busses.

But ANTIC surely must be able to go into tri-state too ? But since it lacks a CS how does this work ?

 

[EDIT] of course ANTIC doesn't have a CS input as it is actually the boss in the whole system.....duh

Edited by Level42

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Wait a minute.....ANTIC can't write to memory so it never writes on the databus....but it does put addresses on the address bus but only does so when it has HALTed Sally, right ? And POKEY, PIA and GTIA are just slaves, they never put address on the addressbus.....

 

So....am I correct that following this there is no need for tri-state buffers on ANTIC ?

Edited by Level42

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Antic's need to use the bus is highly deterministic and depends on graphics mode, screen width, whether PM graphics are in use, if H-Scrolling is enabled and what the HSCROL value is.

 

That aside, the /HALT signal is all that's needed with Sally. In the earlier 400/800 they just used an off-the-shelf 6502B and had a few 74LS chips that were used to hold the 6502 in the bus inactive part of the cycle if Antic wanted the buses.

 

Since cost saving possibilities were identified as time rolled on, Sally was the evolution where Atari requested that feature just be built into the CPU itself. Other IC counts were achieved over time with such chips as the MMU and later Freddie.

 

GTIA also has it's bus cycles though they are done in a passive way. If GTIA has the bits set to load the GRAF registers for PMs, then it will fetch whatever's on the data bus at the start of each scanline. Normally you'd want to enable PM DMA on Antic otherwise you'll get 6502 instruction data or Display List instruction data being used for PM pixels.

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Wait a minute.....ANTIC can't write to memory so it never writes on the databus....but it does put addresses on the address bus but only does so when it has HALTed Sally, right ? And POKEY, PIA and GTIA are just slaves, they never put address on the addressbus.....

 

So....am I correct that following this there is no need for tri-state buffers on ANTIC ?

 

The address bus on the ANTIC is used for both input and output, so when it's not doing output there would be internal circuitry that would stop if from driving the bus so it can read from it.

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Guys thanks for all the great input ! Trying to read as much info as I can everywhere on the net.

Edited by Level42

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You mention GTIA internal schematics ? Where can I find those ? And are they also available for the ANTIC ?

 

I noticed there are links on wikipedia articles about GTIA and ANTIC but those are dead.

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Don't bother with Wikipedia for Atari, it's a mix of information that's wrong and badly plagiarized from various sources.

 

ANTIC datasheet: http://ftp.pigwa.net/stuff/collections/nir_dary_cds/Tech%20Info/ANTIC.PDF

GTIA datasheet and schematics: http://ftp.pigwa.net/stuff/collections/nir_dary_cds/Tech%20Info/GTIA.PDF

POKEY datasheet and schematics: http://ftp.pigwa.net/stuff/collections/nir_dary_cds/Tech%20Info/POKEY.PDF

High-res POKEY schematics: http://www.atarimuseum.com/whatsnew/2016-NOV-2.html

 

The ANTIC datasheet is not worth reading. There's nothing in it that isn't already in the 400/800 Hardware Manual except for the pin specs, which are boring because they're all digital pins. The GTIA and POKEY datasheets are more interesting, but the scan quality on the schematics is so bad that they're impossible to read unless you squint and do a lot of cleanup work. ijor's reverse engineered schematics are much more useful and as far as I can tell, fully correct. You already have the ANTIC one, but for completeness:

 

NTSC GTIA: http://atariage.com/forums/topic/186756-gtia-decap/?p=2357183

POKEY: http://atariage.com/forums/topic/182670-pokey-decap/?p=2290814

 

Unforunately, schematics are still absent for PAL and SECAM GTIAs.

 

ANTIC does have buffers on the address lines in the schematic. They're just not labeled as buffer blocks and are only on A0-A3.

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ANTIC does have buffers on the address lines in the schematic. They're just not labeled as buffer blocks and are only on A0-A3.

 

 

Read the datasheet but it appears to me that all address lines are tri-stated ?

 

Now....when actually does ANTIC decide to activate the HALT ? How is the tri-state condition (high Z) activated on ANTIC ? is there one pin responsible for this or is this an internal process ?

Would removing the input clock(s) activate the Hi-z state on address- and databus ?

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Read the datasheet but it appears to me that all address lines are tri-stated ?

 

Now....when actually does ANTIC decide to activate the HALT ? How is the tri-state condition (high Z) activated on ANTIC ? is there one pin responsible for this or is this an internal process ?

Would removing the input clock(s) activate the Hi-z state on address- and databus ?

 

 

I would assume the address bus would be in input mode whenever it isn't halting the processor since it needs to decode the bus to check for register writes. As for when it activates Halt, check out the Altirra Hardware Reference which has a lot of information about ANTIC timing.

 

http://www.virtualdub.org/downloads/Altirra%20Hardware%20Reference%20Manual.pdf

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Mmmm...sounds logical....I wonder when ANTIC will go in hi tri-state then.......thanks for that link, very clear explanation of a lot of things,....but in the end.... I still don't know when ANTIC actually decides to send the HALT to Sally. I think it might be when something is written to DMACTL register ?

 

I just experimented with switching NTSC and PAL ANTICs. Must say that the feel of speed on f.i. Donkey Kong is the same when a NTSC ANTIC is in a PAL PCB compared to a full NTSC machine......I can't tell the difference of the main clock. Because I'm stubborn I also exchanged the main crystal between the systems and surely enough, as expected, you lose the color....

Edited by Level42

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SO....I decided the proof is in the pudding. I piggy bagged a (PAL) ANTIC onto the NTSC ANTIC that is now in my PAL PCB with all pins bent out except databus and adressbus.

 

The machine works 100%.......

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SO....I decided the proof is in the pudding. I piggy bagged a (PAL) ANTIC onto the NTSC ANTIC that is now in my PAL PCB with all pins bent out except databus and adressbus.

 

The machine works 100%.......

 

Oooh... I like where I think this is going! :)

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SSshhhhhhh :D

 

 

 

Right.... via trial and error I learned that the ANTIC/A8 don't seem to mind having these lines connected "in parallel". (See picture).

 

The others are either outputs (which I won't even try to connect together directly because it feels stupid to do so) OR show problems when I do piggy-back them....

 

The ones NOT connected in parallel are:

 

AN0,1,2 - Interface to to GTIA, I didn't try to piggy-back them because I don't think it would be a good idea....they seem to be completely steady on the piggy-backed ANTIC. I think not putting in any clock signals keeps ANTIC "silent" (and hopefully in hi-Z state)

NMI (this is an output...don't want to connect. RNMI is an input which is permanently connected to +5V in XLs so no problem connecting that)

REF = RAM refresh output....feels silly to piggy-back those...not a good idea...

HALT = of course another output. We want only 1 ANTIC to be boss on the buss....not two :)

R/W = input, tried to piggy back but machine boots with red/brown screen....
RDY = ready output....yet another output which I don't want to connect...

Ph2 = clock input. Not inputting anything seems to "freeze" ANTIC...good idea to not piggy-back

Ph0 = output...again, no outputs in piggy-back...

FPh0 = Fast clock input....better not connect that either.

 

I'm not sure yet about the RST pin....seems to work sometimes, needs a bit more experimenting.

 

I can load games (Tried Donkey Kong, Master of the Lamps and Blue Max) without a problem from SIO2PC-USB.

 

I already noticed one weird behavior though.....when I move my finger close to the piggy backed ANTIC, the display screws up. I'm sure some input is floating and my finger in the neighborhood is enough to trigger something.

 

Guess some unused inputs are better tied to ground or +5V to prevent this behavior.

 

 

I also notice that a Power-down, Power-up cycle needs a bit more time than normally to boot stable...

 

Still lots of experimenting to do, but happy so far...

post-25272-0-45075200-1505170049_thumb.jpg

Edited by Level42
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Mmmm...sounds logical....I wonder when ANTIC will go in hi tri-state then.......thanks for that link, very clear explanation of a lot of things,....but in the end.... I still don't know when ANTIC actually decides to send the HALT to Sally. I think it might be when something is written to DMACTL register ?

 

I just experimented with switching NTSC and PAL ANTICs. Must say that the feel of speed on f.i. Donkey Kong is the same when a NTSC ANTIC is in a PAL PCB compared to a full NTSC machine......I can't tell the difference of the main clock. Because I'm stubborn I also exchanged the main crystal between the systems and surely enough, as expected, you lose the color....

 

ANTIC sends the Halt when it needs to read from memory. These memory reads happen at specific times during each scanline. As the documentation I linked to shows, the exact pattern on the memory reads is dependent on the scanline graphics mode and other configuration settings.

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OK... I figured out which pin was sensitive for my finger :)

 

https://youtu.be/ZUooN_ZY-Ik

 

I also just tried piggybacking the Antic on my 600XL. Of course this also works fine.....however, now I could try it with a cartridge (the 800XL is temporarily lacking a cartridge port) and the game doesn't start with the piggy backed ANTIC....

 

Any ideas why cartridges wouldn't work while everything else does work just fine ?

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Correction:

 

Cartridge works just fine.

Good news. I was hoping it wasn't the infamous "unstable Phi2" bus issues which come into play with multiple mods in a machine.

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What's the purpose of this piggybacking? I suspect that 2 Antics might work in lockstep but a potential problem is that the startup could be variable between the two so they might be a quarter of a scanline apart or something. That would throw DMA timing out.

 

Note there's 2 labelled resets on Antic - one was an output to /NMI for the System Reset key on 400/800.

 

The hardware reset - unsure if it's used outside powerup or at all. The thing with Antic is that it and GTIA seem to remain at least partially active during a hardware reset. You can illustrate this by holding the Reset key down on an XL. If the reset stopped those chips then the display would falter and it doesn't. GTIA can autonomously maintain HSync timing but needs to be told by Antic when to do a VSync.

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DanBoris.....that would be giving away the fun.....and I will look stupid if I fail :)

 

drac030: hahaaaaa, hate to disappoint you....nothing fried here. First of all: I'm using a PAL for my experiments (the one with the bent out pins) because I have only one NTSC ANTIC which is in my NTSC 800XL but I have plenty of 600XLs to choose a PAL ANTIC from....which I did.....

 

No, I need another NTSC ANTIC for my experiments.....

 

I can't believe that no-one except Adam242 has an idea where this is going.....it's so obvious.... :)

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I would guess he might have wanted to fry something. And succeeded http://atariage.com/forums/topic/270020-looking-for-1-or-ntsc-antics-preferably-somewhere-around-holland/

 

;)

 

Sometimes the price you pay for trying to develop a new idea. I should know, I fried 2 U1MB boards. One because I used a smaller interface plug (fewer pins) and during one of the VGATE board installs I accidentally got it shifted by one pin position which put 5V into one of the CLPD I/O pins. The other time was very recent during 1088XEL testing when one of the mini-alligator clips I had attached to the MPBI port's 5V connection rotated and hit a CPLD I/O pin routed to that bus. I would much rather fry Antic chips which I have a bunch of (and are relatively cheap), than U1MB's which makes for an expensive mistake.

 

- Michael

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