6502 not technically RISC, but sure looks like it sometimes

[rpiguy9907]

I know the 6502 and family are CISC processors with complex addressing modes, fixed stack, and direct memory operations, but if you look at the attached benchmark of early microprocessors you can see why some called it the first RISC processor.

 

The 6502 requires MORE instructions to complete the operation than its competitors, but because many instructions execute in 1 clock cycle, it beat the pants off of the other chips. That was part of the RISC philosophy, use fast, simple instructions over complex instructions.

 

I imagine the TMS 9900 either had a multiply unit, or the benchmark was 16-bit multiplication, in which case the 16-bit TMS 9900 would naturally beat the 8-bitters.

 

TMS 9900 had some sexy code density for whatever algorithm they used for this benchmark. The king of 1970s CISC!

Edited March 9, 2018 by rpiguy9907

[JamesD]

The 6502 isn't much different from the 6800 except for the instruction prefetch.
That is certainly one of the features of RISC, but RISC normally has a full pipeline, cache, a large number of general purpose registers, an orthogonal instruction set, and a load & store architecture... none of which are on the 6502.
The original spec for RISC also called for 32 bit registers, but later editions of the book by the creators of RISC quietly dropped that comment, and there are smaller and larger RISC processors now.
So really, the 6502 only has one of the RISC features.

Frankly, without the instruction prefetch, the 6502 probably wouldn't have had much success because it would have been slower than the competition, and it wasn't much cheaper once Motorola and Intel dropped prices. At the time, it made the 6502 very competitive.

Not being RISC isn't a bad thing. Given the instruction set, I doubt it would gain much from a full pipeline, and lot of general purpose registers would have made it expensive.

A load and store architecture would have actually made it slower. You have to load data into a register before you can do something with it. You can't directly use something from memory.

A true RISC chip usually takes at least 3-4 clock cycles per instruction (much more with floating point), but the pipeline makes the throughput about 1 instruction per clock cycle since it is processing multiple instructions in the pipe. But when there's an interrupt... there's latency.

So it's probably a good thing the 6502 isn't RISC.

Since superscaler tech, out of order execution, etc... etc... etc... were introduced, CISC derivatives have been introduced that are faster than RISC equivalents, while having smaller code. RISC was really a solution for that time, but now the only advantage it has is a smaller core than CISC competitors. That does make it low power though. That's why it has been so popular in small electronics, but why it hasn't dominated the workstation/desktop computer market.

[carlsson]

I'd say the 6502 takes 2-6 cycles per instruction but even that is little in comparison. If you run it at 2 MHz, it would be 1-3 us/instruction.

[phoenixdownita]

@james the 6502 is a load and store (lda,sta) it is a RISC like in many regards but it does lack some.

Also just to stay in x86 land I think you are aware that the CISC instructions get translated in RISC like for the real internal architecture. It has been the case for the past 20y or so (Pentium pro or whenabouts)

[landgraf]

@james the 6502 is a load and store (lda,sta) it is a RISC like in many regards but it does lack some.

Yes, but it can also modify memory directly (asl, lsr, ror, rol, inc, dec), which is a big no-no for true RISC architectures.

[carlsson]

Doesn't nearly every CPU have an accumulator or two? LDA simply loads values into the accumulator and STA stores them into a memory location. You can also use the two registers X and Y in similar ways, but perhaps that is also a RISC-y property that on-CPU registers no matter how many they are, can be loaded and stored directly against memory without going through the accumulator?

[JamesD]

@james the 6502 is a load and store (lda,sta) it is a RISC like in many regards but it does lack some.

Also just to stay in x86 land I think you are aware that the CISC instructions get translated in RISC like for the real internal architecture. It has been the case for the past 20y or so (Pentium pro or whenabouts)

landgraf is correct.

 

A load and store architecture does not mean it has load and store instructions.

Load and store from / to memory are completely separate from other operations.

 

6502, if you want to add a number at address $44 to the accumulator and store it back in $44

; accumulator is already loaded with a value

adc $44 ;add directly to accumulator from address $44

sta $44 ;store result in address $44

 

Load and store would look more like this

;R0 is already loaded with a value

ld R1,$44 ; load value from address $44 into R1

add R0,R1 ; add R1 to R0

st $44,R0 ; store result in address $44

 

You cannot directly add, subtract, etc... from memory or to memory without going through registers.

This greatly simplifies the design.

 

 

And x86 translates to a microcode, but it doesn't necessarily have the same limits as a pure RISC design.

It doesn't even require all code go through a single pipeline.

[JamesD]

Doesn't nearly every CPU have an accumulator or two? LDA simply loads values into the accumulator and STA stores them into a memory location. You can also use the two registers X and Y in similar ways, but perhaps that is also a RISC-y property that on-CPU registers no matter how many they are, can be loaded and stored directly against memory without going through the accumulator?

Part of the deal with RISC is registers are general purpose.

All instructions work with all registers. So there are no accumulators or index registers, there are just a lot of registers that can be used with every instruction.

It's about simplifying the pipeline, simplifying instruction decoding, and reducing the number of special cases for each instruction.

[carlsson]

So well, based on these combined facts, the 6502 (and the 6800 it was based on) for sure don't qualify as RISC architectures. Perhaps "reduced" in that they have fewer registers and not as complex instructions as some of the other CPUs of the time - I'm mainly thinking about 8080/Z80 and TMS-9900 but there may be others to consider as well - but limited repertoire and low amount of cycles per instruction clearly are not the only features of a RISC.

[JamesD]

So well, based on these combined facts, the 6502 (and the 6800 it was based on) for sure don't qualify as RISC architectures. Perhaps "reduced" in that they have fewer registers and not as complex instructions as some of the other CPUs of the time - I'm mainly thinking about 8080/Z80 and TMS-9900 but there may be others to consider as well - but limited repertoire and low amount of cycles per instruction clearly are not the only features of a RISC.

RISC is really a bad acronym for what it really is. It's very misleading.

It's not so much that it is reduced, but how it's reduced, and it completely ignores all the other architecture requirements.

 

 

 

Nobody should feel bad for not knowing this stuff.

This was taught in a 500+ level computer science class at the university I was at, and it wasn't even a required class for most IT degrees.

The book we used was only used for the CS class that one time because it was so technical from a hardware standpoint.

After that it was only used for a graduate EE class.

One thing is for sure, I've never read most of the explanation for what RISC is outside of that class.

[carlsson]

Yeah. Probably the most common thought is that RISC is faster than CISC, irregardless of all other aspects.

[phoenixdownita]

Not claiming the 6502 is RISC per se but it does have a definite RISC like flavor to it if you make the leap of faith and consider page0 really like a 256 long register file. With this adjustment the 6502 is a bit of a forerunner (albeit it still lacks some attributes).

 

Not trying to convince you but to be fair RISC was defined early 1980 while 6502 is a child of the mid 1970 so aside some similarity claiming one way or another is moot.

 

 

EDIT: as we are at it http://forum.6502.org/viewtopic.php?t=720

[JamesD]

Well, you have to understand that every technology used in RISC, existed before RISC. So having one or two features doesn't make it RISC like.
It just means it borrowed from earlier designs, mostly the PDP-11.

RISC tied several different processor features together, and that combination provided a much faster and more efficient result than when those concepts are used separately.
It's the combination of those features that made it unique and makes something RISC.
You also have to consider WHY they chose that approach.
One of the key benefits of the design, was simplifying compiler construction.
Compiler technology was... well... to be honest it was primitive.
General purpose registers, orthogonal instruction set, simplified pipeline due to load and store architecture, etc... makes it easier to build a compiler and to generate efficient code.

The original papers that were published on the subject, were a discussion over how to make processors better for compiled languages.
There were two proposed approaches. Simplifying the design to make it easier to generate the code, but make up for it with fast throughput, or adding more specialized instructions just for compiler support.
This is where 8 bit processors completely fail.
Even though the 6809 supports compilers fairly well, generating code for it is a lot more complex than RISC.
And the 6502 makes the 6809 look spectacular in comparison from that standpoint.

[JamesD]

Actually, I looked up the PDP-11, and the 6800/6502 instructions are inspired by it, but the register setup looks like something else.

Edited March 11, 2018 by JamesD

[rpiguy9907]

Well the 6502 register setup was inspired by the 6800, but the MOS guys realized that a second index register was more useful than a second accumulator and cheaper as well.

 

The 6800 I believe was inspired by HP stack machines and Boroughs computers.

Edited March 11, 2018 by rpiguy9907

[JamesD]

The Burroughs I found looks very different.
Not sure which HPs you mean.

The Data General Nova had two accumulators and two index registers.

[rpiguy9907]

HP 2100 family of stack machines. NOVA also is similar to the HP 2100 so that is also possible. I believe the Boroughs small systems were accumulator stack machines. I will try to dig out the quote for this being an inspiration if I can find it. I may be misremembering.

[JamesD]

If you can't find it, that's okay.
The important thing, is that people understand these CPUs were inspired by earlier designs and don't include features unique to RISC.
The 8 bit CPUs really don't have any new technology. They are mostly different in that:
1) The CPUs are IC's instead of discrete logic. This transition was also taking place on minicomputers.
2) They are only 8 bit, where most minicomputers and mainframes use 12, 16, or more bits.
3) A person might have had to save up to buy a computer based on one, but the average person could afford one.


If you read the info on some of these minicomputers, you'll see RAM sized as small as 4K and fully expanded sizes of 64K (32K words).
While that may sound small, the systems usually ran batches of data and programs weren't really large.
It doesn't take a lot of RAM to run through a list of employee time sheet info stored on disk, calculate total hours, calculate total pay before taxes, calculate tax & social security withholding, and then print checks.
A compiled program could probably do that in 4K since all the the data you are currently using resides on disk.
The calculations may have even been done in different batches than printing the checks.

[thetick1]

The first RISC processor was designed by IBM in 1974 call 801 processor. My first manager at IBM was on that first RISC design team. It was used as a custom storage controller processor for mainframes and it was not of any real significance at the time. It was not called RISC until later when the same architecture was used by IBM in late 80's for their first workstation IBM RT PC. That cpu was the IBM ROMP processor predecessor to all the IBM POWER and PowerPC processors including the Playstation 3. Cell processor, Xbox 360 Xenon processor and many Nintendo GameCube, Wii, Wii U processors.

 

See http://www-03.ibm.com/ibm/history/ibm100/us/en/icons/risc/

 

Anyway JamesD is right as RISC is really misleading especially now days. Back back in the 80's ,90's there were CISC (Complex instruction ) ie all the mainframes, VLIW (never really used outside research except the failed Itanium designs) and RISC was just name used to describe the competing architecture. RISC has pipeline lined optimized, high percentage of general register to register operations and optimized cache designs.

 

And as phoenixdownita mentioned all modern cpus (from mainframes down to embedded controllers and cellphones) execute RISC operations even if the processor is implementing a CISC architecture.

Edited March 11, 2018 by thetick1

[rpiguy9907]

This is why I was very clear in the first sentence of my post to say 6502 is clearly CISC and that it really only feels like RISC because of the simpler/faster is better philosophy. All the execution characteristics are CISC. I never meant for this thread to turn into a discussion of whether it was RISC or not, lol.

 

If you can't find it, that's okay.

The important thing, is that people understand these CPUs were inspired by earlier designs and don't include features unique to RISC.

The 8 bit CPUs really don't have any new technology. They are mostly different in that:

1) The CPUs are IC's instead of discrete logic. This transition was also taking place on minicomputers.

2) They are only 8 bit, where most minicomputers and mainframes use 12, 16, or more bits.

3) A person might have had to save up to buy a computer based on one, but the average person could afford one.

 

 

If you read the info on some of these minicomputers, you'll see RAM sized as small as 4K and fully expanded sizes of 64K (32K words).

While that may sound small, the systems usually ran batches of data and programs weren't really large.

It doesn't take a lot of RAM to run through a list of employee time sheet info stored on disk, calculate total hours, calculate total pay before taxes, calculate tax & social security withholding, and then print checks.

A compiled program could probably do that in 4K since all the the data you are currently using resides on disk.

The calculations may have even been done in different batches than printing the checks.

Edited March 12, 2018 by rpiguy9907

[JamesD]

Title of the thread:

6502 not technically RISC, but sure looks like it sometimes

[thetick1]

 

Title of the thread:

6502 not technically RISC, but sure looks like it sometimes

 

 

The 6502 more like a microcontroller than a RISC processor.

[JamesD]

 

The 6502 more like a microcontroller than a RISC processor.

The 6502's 8 bit everything makes a lot of sense in a microcontroller.

 

[The Usotsuki]

There are 6502 and 65816-based microcontrollers.

[zzip]

I know the 6502 and family are CISC processors with complex addressing modes, fixed stack, and direct memory operations, but if you look at the attached benchmark of early microprocessors you can see why some called it the first RISC processor.

 

The 6502 requires MORE instructions to complete the operation than its competitors, but because many instructions execute in 1 clock cycle, it beat the pants off of the other chips. That was part of the RISC philosophy, use fast, simple instructions over complex instructions.

 

I imagine the TMS 9900 either had a multiply unit, or the benchmark was 16-bit multiplication, in which case the 16-bit TMS 9900 would naturally beat the 8-bitters.

 

TMS 9900 had some sexy code density for whatever algorithm they used for this benchmark. The king of 1970s CISC!

One of the other characteristics of RISC processors is lots of general-purpose registers. The 6502 certainly falls short on that front.