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Icy99 FPGA 99/4A

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Again it's been a long while since I wrote anything here...

I thought to write a short update about my work on my new FPGA version of the TI-99/4A. This is work in progress.

 

In short, I'm in the process of creating a version for the Blackice-II FPGA board. This is an affordable board (I hope it is still available) with a fairly small ICE40HX4K FPGA chip, 512K RAM and a fairly powerful microcontroller. The board is supported by the open source Icestorm toolchain, and I have used that for development work.

 

This has been an interesting adventure so far.  Icestorm very nice and compact toolchain compared to the bloated Xilinx and Altera tools. However, Icestorm only supports the Verilog hardware description language, so I had to learn Verilog and port my existing VHDL code base to Verilog.

 

Most of the work so far (and I have but a fair amount of hours into this already) has gone to porting and modifying the code to work on this fairly limited platform, changing the language to Verilog and designing around the limitations.

 

In the context of recreating the TI-99/4A the biggest drawback is that the small FPGA only has 16K of internal RAM (compared to 64K on the chip I used for the VHDL version). Also, the internal RAM is a lot less sophisticated. The result has been that I have had to redesign the system architecture quite a bit, so that the external 512K RAM chip is now used for code, data and video memory - as opposed to using on-chip RAM for video memory in the past. This may seem like a small change, and in a way it is, but in practice I had to design a much more involved memory controller which can arbitrate between CPU, VDP, and the bootloader accesses in real time.

 

Although I have converted my whole code base to Verilog, currently only a portion of this has been fully ported and works. Namely I have a system now that has the TMS9900 CPU, TMS9918 VDP with VGA output, memory controller driving the external RAM, EVM-BUG debugger in a 8K ROM block, and finally pnr's TMS9902 UART.

 

The ICE40HX4K chip is only supposed to have 4K LUTs (look up tables), but in practice the silicon is the same as ICE40HX8K with 7680 LUTs  and the Icestorm toolchain enables access to all of them. Which is good, since the design already uses 4421 LUTs. The design runs at 25MHz, which is the VGA pixel clock. I am hoping I can fit in the whole thing into this FPGA. As the chip's resources gets close to full utilization the routing probably becomes impossible, so I cannot add too much more. I don't know yet where the limit is.

 

One of the consequences of having the VDP use external RAM is that it now is possible to map video RAM to CPU's address space directly, and that is what I have done during debugging (I'm not yet using TI-99/4A ROMs, just EVMBUG). There are now two ways to access VRAM: using the standard indirect registers - this is obviously necessary for compatibility, and alternatively by just directly mapping it to CPU address space. Direct access to VRAM vastly increases the bandwidth and makes it very easy to use, but of course no existing software supports this...

 

Next I need to add GROM support, which should be easy. When that is in place I should be able to boot this thing with the TI-99/4A ROMs. I still need to figure out how to split the 512K RAM between different functions, probably something like this:

8K system ROM  (0000..1FFF)

8K disk support  (4000..5FFF)

256K paged cartridge space (6000..7FFF)

64K GROM space (24K used by console GROM [actually 18K but multiplies of 2 are easier])

64K VRAM space

32K normal RAM expansion

That leaves 80K still to be allocated to something. If I can fit in my memory paging unit, it probably would make sense to have the ability to configure either 256K AMS memory space or 256K cartridge space.

 

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It looks like a very interesting project! 🙂 I have some questions regarding your project and the BlackIce board.

 

Do you plan to implement also the disk and speech support in order to have a complete TI99 system in FPGA?

 

The second question is related to the board used for the implementation. What's the main reasons for the choice? What are the advantage over other more common solutions used for retrocomputing? In particular, I'm referring to the use of a De10-Nano of the MiSTer project. You'll be probably aware that your EP994A code was converted for MiSTer and is running quite fine, although the implementation is missing disk and speech support. So, why not starting from that point to implement a more complete FPGA solution for our TI99?

 

At the end of the project the BlackIce board will permit to run a TI99 FPGA solution in a standalone manner, similar to MiSTer/Mist? Or it will require to be always connected to a PC to be operable (e.g. to load a new SSS module, etc.)?

 

I think that a lot of TI fans are expecting a implementation of our TI99 in FPGA, similar to those available for other systems like the C64 for completeness and robustness. It's the "orphan" syndrome since 1983.. 🙂

 

Many thanks for your work and support to the TI community and please keep us updated with the progresses! 🙂

 

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BlackIce MX has fewer GPIO pins (48), and replaces static RAM with SDRAM. So you need some more code before you can get RAM up and running.

 

The BlackIce II went out of stock more than a year ago. MX is about the same price. MX was created to be more friendly to builders who want to drop it into their own "carrier" board alternate to the simple one provided.

 

I had a triple-PMOD on BlackIce II connected to the 4A side port, providing SAMS memory and memory mapped devices. I had to redesign it for MX to use just 16 pins, but I'm still using it on the II for the static memory.

 

 

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On 10/12/2019 at 11:46 PM, Ksarul said:

Looks like the current product is the Blackice Mx. It seems to be using the same FPGA though.

Yes, I am aware of the Mx and in fact I have one. I just started to work with the Blackice II, for two reasons: I have several of them, and working with SRAM is easier than SDRAM. Having said that, I have ported an earlier design of mine to a cheap Xilinx board with SDRAM. That design uses SDRAM but comprises of the TMS9900 and UART only, it is my test bed for SDRAM work.

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On 10/13/2019 at 10:29 AM, tmop69 said:

It looks like a very interesting project! 🙂 I have some questions regarding your project and the BlackIce board.

 

Do you plan to implement also the disk and speech support in order to have a complete TI99 system in FPGA?

 

The second question is related to the board used for the implementation. What's the main reasons for the choice? What are the advantage over other more common solutions used for retrocomputing? In particular, I'm referring to the use of a De10-Nano of the MiSTer project. You'll be probably aware that your EP994A code was converted for MiSTer and is running quite fine, although the implementation is missing disk and speech support. So, why not starting from that point to implement a more complete FPGA solution for our TI99?

 

At the end of the project the BlackIce board will permit to run a TI99 FPGA solution in a standalone manner, similar to MiSTer/Mist? Or it will require to be always connected to a PC to be operable (e.g. to load a new SSS module, etc.)?

 

I think that a lot of TI fans are expecting a implementation of our TI99 in FPGA, similar to those available for other systems like the C64 for completeness and robustness. It's the "orphan" syndrome since 1983.. 🙂

 

Many thanks for your work and support to the TI community and please keep us updated with the progresses! 🙂

 

Thanks a lot for these comments and questions! These are really good ones.

 

Regarding the choice of FPGA board. For this second design, I really wanted to try out the open source tool chain, and since that only support Lattice chips, I am stuck with those. However, there are important implications:

  • Since the ICE40HX chips are primitive in FPGA standards, the design work that I have done now includes almost no platform dependent code. As an example, the multiplier is now implemented in verilog. That means that this second version of the design is very portable.
  • I plan to implement this version of the design on multiple FPGA boards. I have now a whole bunch of FPGA boards (too many in fact, I don’t know how many), including MIST and MISTer. Of these I have not even powered on the MISTer yet...
  • Even though I am working with FPGAs which by definition are new and not retro, I think it still is somehow in the spirit of retro computers to try to use a solution with limited resources. The MISTer is very cool but has huge resources compared to what a complete and expanded TI-99/4A needs. I admit that this point is a bit philosophical, but this work is more interesting for me if I learn and get challenged along the way, rather than just porting the same stuff over and over again.

And yes, I want to make this standalone. My previous design already can run in standalone mode, but it required help from a microcontroller board. I have implemented a version of file system support, which supports storing TI files in a FAT file system.

 

Since my last message I have added GROM support, but there is currently a bug which only shows up when running on hardware, in simulation it works perfectly as far as I can tell. So limited progress but still some progress.

 

Finally, in the spirit of going simple, for this design I removed the cache and I plan to also make a cycle accurate version of the TMS9900 CPU. My original aspiration was to make my “dream TI” as in making a TI-99/4A that can go very fast, and got reasonably close to that already with 30x original speed and beyond. Having done that I realize that I also want go slow, close to original speed.

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On 10/15/2019 at 11:48 PM, FarmerPotato said:

BlackIce MX has fewer GPIO pins (48), and replaces static RAM with SDRAM. So you need some more code before you can get RAM up and running.

 

The BlackIce II went out of stock more than a year ago. MX is about the same price. MX was created to be more friendly to builders who want to drop it into their own "carrier" board alternate to the simple one provided.

 

I had a triple-PMOD on BlackIce II connected to the 4A side port, providing SAMS memory and memory mapped devices. I had to redesign it for MX to use just 16 pins, but I'm still using it on the II for the static memory.

 

 

I have the MX so I know it’s specs, although I am saving it for later. The current version has problems with its HDMI connector. I did not know that BlackIce II is history - that is a shame, I like that board. Thanks for letting me know, I assumed they would still be available.

 

The BlackIce II thing you’ve made sounds similar to what I did with the Pipistrello 64M memory expansion for the 4A. Have you published your design?

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