Internal memory mod

[+OLD CS1]

On 9/2/2021 at 10:58 AM, apersson850 said:

I've also never used a Commodore 64 in any depth, but I do know it had a similar capability. It could be 64 K RAM, but not at the same time as having access to all system services.

The 64's memory map is pretty simple. RAM always exists at all locations from $0002-$FFFF. $00 & $01 are consumed in the 6510's map by its built-in I/O port which controls cassette functions and the memory map, although the RAM can still be read and written by the VIC-II or DMA controller like in the REU.

 

ROM can be mapped in at various locations around the memory map: cartridge ROM at $8000, BASIC at $A000, KERNAL at $E000.  When ROM is mapped in, reading the space will return ROM values, while writing puts into RAM "under" the ROM.  I/O space is $D000-$DFFF and when mapped in, RAM is unavailable in these ranges.  Note that, as with the TI's 8k cartridge space from >6000 to >7FFF, the 64's 8k cartridge space at $8000 can also be bank-switched.

 

This is nowhere near as fancy as the 128's memory banking techniques with its sophisticated MMU, and simple relative to the TI's SAMS memory banking scheme. Fortunately on the 64, no RAM or mapped devices sit behind wait-states, although the VIC-II video chip can force the CPU to wait if more time is needed for video data fetches from RAM.

 

In this configuration it is possible to run with a full contiguous 64k RAM, until the system needs access to the outside world, at which point the I/O devices must be mapped in.

[apersson850]

Thanks for the tutorial.

I deliberately avoided shadow-RAM, since the TI has not only ROM, but also memory-mapped IO at some of the standard addresses. This means that copying ROM can't be done just by MOV *R1,*R1+. You either have to toggle ROM/RAM between each word, or copy the whole 8 K bank to a RAM bank at some other address, then enable RAM over ROM and write it back again.

In my design, the bank switch bits are inverted for the standard 32 K RAM expansion areas. Thus the console wakes up with internal RAM at 2000-3FFF and A000-FFFF. The remaining RAM is disabled. For the remaining RAM you do SBO to turn it on, but SBO turns the standard 32 K RAM off.

[+mizapf]

8 hours ago, OLD CS1 said:

The 64's memory map is pretty simple. RAM always exists at all locations from $0002-$FFFF.

Not to get too far off-topic, but at that occasion I'd like to ask how the 6502/6510 deals with 16 bit addresses while its ALU is only 8 bit wide. The TI can easily handle all addresses of its address space because of the 16-bit ALU.

[TheMole]

I wonder if anyone has ever considered making a full-address space 16-bit RAM expansion with SAMS compatible bank switching + plus the ROM overlays ala @apersson850's 16-bit RAM. I'm imagining replacing the CPU with a socket and moving the CPU to a PCB that contains the RAM expansion and plugs in to the newly added CPU socket. Sort of like the way certain Amiga RAM expansions work.

 

I know desoldering a 64 pin DIP IC is not for the faint of heart, but a 'wireless' solution like that (one that doesn't require any bodge wires) might be a more elegant solution to some (i.e. me).

 

IANAHWG (I Am Not A HardWare Guy), but it might be a fun project to tackle.

[apersson850]

2 hours ago, mizapf said:

Not to get too far off-topic, but at that occasion I'd like to ask how the 6502/6510 deals with 16 bit addresses while its ALU is only 8 bit wide. The TI can easily handle all addresses of its address space because of the 16-bit ALU.

Short answer is "in various complicated ways".

 

Some details:

Zero page addressing is one way. There the high 8 bits are assumed to be zero, so you get 256 bytes you can access.

Absolute addressing, where the instruction is followed by two bytes, specifying a 16-bit address, is another.

Indexed addressing, where the instruction is followed by one byte, which is a zero-page address to a 16-bit base address, which is added to the content of the 8-bit Y register, as an 8-bit offset (index) from that base address, is a third.

Indexed addressing, where the instruction is followed by a byte, which is added to the content of the 8-bit X-register, to form a combined zero page address, where the actual 16-bit address is found, is a fourth.

 

There are very few registers in the 6502, and except the PC (program counter, pointer to next instruction), they are all 8-bit. Accumulator, X and Y index registers and stack pointer are the rest. Yes, the status register too, of course, but it's not for general use.

Note that the stack pointer is also 8-bit. The stack address always starts with 01 in the first byte, so the stack occupies 0100-01FF.

 

The TMS 9900 is just lovely to write programs for, in comparison.